FCB for lpc5536, Revision: 1a and flexspi_nor

Type: object

root family

The chip family name

Type: enum (of string)

NXP chip family identifier.

Must be one of:

  • "lpc5534"
  • "lpc5534"
  • "lpc5536"
  • "lpc5536"
  • "lpc55s36"
  • "lpc55s36"
  • "mcxn546"
  • "mcxn546"
  • "mcxn547"
  • "mcxn547"
  • "mcxn946"
  • "mcxn946"
  • "mcxn947"
  • "mcxn947"
  • "mimxrt1010"
  • "mimxrt1015"
  • "mimxrt1020"
  • "mimxrt1024"
  • "mimxrt1040"
  • "mimxrt1043"
  • "mimxrt1046"
  • "mimxrt1050"
  • "mimxrt1060"
  • "mimxrt1064"
  • "mimxrt1165"
  • "mimxrt1166"
  • "mimxrt1171"
  • "mimxrt1172"
  • "mimxrt1173"
  • "mimxrt1175"
  • "mimxrt1176"
  • "mimxrt1181"
  • "mimxrt1181"
  • "mimxrt1182"
  • "mimxrt1182"
  • "mimxrt1187"
  • "mimxrt1187"
  • "mimxrt1189"
  • "mimxrt1189"
  • "mimxrt533s"
  • "mimxrt533s"
  • "mimxrt555s"
  • "mimxrt555s"
  • "mimxrt595s"
  • "mimxrt595s"
  • "mimxrt685s"
  • "mimxrt685s"
  • "mimxrt735s"
  • "mimxrt735s"
  • "mimxrt735s"
  • "mimxrt758s"
  • "mimxrt758s"
  • "mimxrt758s"
  • "mimxrt798s"
  • "mimxrt798s"
  • "mimxrt798s"
  • "rw610"
  • "rw610"
  • "rw612"
  • "rw612"
  • "lpc553x"
  • "lpc55s3x"
  • "mcxn9xx"
  • "mcxn94x"
  • "rt1010"
  • "rt1015"
  • "rt102x"
  • "rt104x"
  • "rt105x"
  • "rt106x"
  • "rt116x"
  • "rt117x"
  • "rt118x"
  • "rt5xx"
  • "rt6xx"
  • "rt7xx"
  • "rw61x"

root revision

MCU revision

Type: enum (of string)

Revision of silicon. The 'latest' name, means most current revision.

Must be one of:

  • "0a"
  • "1a"
  • "latest"

root type

Memory type

Type: enum (of string)

Specify type of memory used by FCB description.

Must be one of:

  • "flexspi_nor"

root fcb_settings

lpc5536

Type: object

root fcb_settings tag

tag


Offset: 0x00000000, Width: 32b; [0x000-0x003] Tag, fixed value 0x42464346UL

root fcb_settings tag oneOf item 0
Type: string or number
root fcb_settings tag oneOf item 1
Type: object
No Additional Properties

root fcb_settings tag oneOf item 1 value
Type: string or number

root fcb_settings field000

tag


Offset: 0x00000000, Width: 32b; [0x000-0x003] Tag, fixed value 0x42464346UL

root fcb_settings field000 oneOf item 0
Type: string or number
root fcb_settings field000 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field000 oneOf item 1 value
Type: string or number

root fcb_settings version

version


Offset: 0x00000004, Width: 32b; [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix

root fcb_settings version oneOf item 0
Type: string or number
root fcb_settings version oneOf item 1
Type: object
No Additional Properties

root fcb_settings version oneOf item 1 value
Type: string or number

root fcb_settings field004

version


Offset: 0x00000004, Width: 32b; [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix

root fcb_settings field004 oneOf item 0
Type: string or number
root fcb_settings field004 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field004 oneOf item 1 value
Type: string or number

root fcb_settings reserved0

reserved0


Offset: 0x00000008, Width: 32b; [0x008-0x00b] Reserved for future use

root fcb_settings reserved0 oneOf item 0
Type: string or number
root fcb_settings reserved0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved0 oneOf item 1 value
Type: string or number

root fcb_settings field008

reserved0


Offset: 0x00000008, Width: 32b; [0x008-0x00b] Reserved for future use

root fcb_settings field008 oneOf item 0
Type: string or number
root fcb_settings field008 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field008 oneOf item 1 value
Type: string or number

root fcb_settings readSampleClkSrc

readSampleClkSrc


Offset: 0x0000000C, Width: 8b; [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3

root fcb_settings readSampleClkSrc oneOf item 0
Type: string or number
root fcb_settings readSampleClkSrc oneOf item 1
Type: object
No Additional Properties

root fcb_settings readSampleClkSrc oneOf item 1 value
Type: string or number

root fcb_settings field00C

readSampleClkSrc


Offset: 0x0000000C, Width: 8b; [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3

root fcb_settings field00C oneOf item 0
Type: string or number
root fcb_settings field00C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field00C oneOf item 1 value
Type: string or number

root fcb_settings csHoldTime

csHoldTime


Offset: 0x0000000D, Width: 8b; [0x00d-0x00d] CS hold time, default value: 3

root fcb_settings csHoldTime oneOf item 0
Type: string or number
root fcb_settings csHoldTime oneOf item 1
Type: object
No Additional Properties

root fcb_settings csHoldTime oneOf item 1 value
Type: string or number

root fcb_settings field00D

csHoldTime


Offset: 0x0000000D, Width: 8b; [0x00d-0x00d] CS hold time, default value: 3

root fcb_settings field00D oneOf item 0
Type: string or number
root fcb_settings field00D oneOf item 1
Type: object
No Additional Properties

root fcb_settings field00D oneOf item 1 value
Type: string or number

root fcb_settings csSetupTime

csSetupTime


Offset: 0x0000000E, Width: 8b; [0x00e-0x00e] CS setup time, default value: 3

root fcb_settings csSetupTime oneOf item 0
Type: string or number
root fcb_settings csSetupTime oneOf item 1
Type: object
No Additional Properties

root fcb_settings csSetupTime oneOf item 1 value
Type: string or number

root fcb_settings field00E

csSetupTime


Offset: 0x0000000E, Width: 8b; [0x00e-0x00e] CS setup time, default value: 3

root fcb_settings field00E oneOf item 0
Type: string or number
root fcb_settings field00E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field00E oneOf item 1 value
Type: string or number

root fcb_settings columnAddressWidth

columnAddressWidth


Offset: 0x0000000F, Width: 8b; [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet

root fcb_settings columnAddressWidth oneOf item 0
Type: string or number
root fcb_settings columnAddressWidth oneOf item 1
Type: object
No Additional Properties

root fcb_settings columnAddressWidth oneOf item 1 value
Type: string or number

root fcb_settings field00F

columnAddressWidth


Offset: 0x0000000F, Width: 8b; [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet

root fcb_settings field00F oneOf item 0
Type: string or number
root fcb_settings field00F oneOf item 1
Type: object
No Additional Properties

root fcb_settings field00F oneOf item 1 value
Type: string or number

root fcb_settings deviceModeCfgEnable

deviceModeCfgEnable


Offset: 0x00000010, Width: 8b; [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable

root fcb_settings deviceModeCfgEnable oneOf item 0
Type: string or number
root fcb_settings deviceModeCfgEnable oneOf item 1
Type: object
No Additional Properties

root fcb_settings deviceModeCfgEnable oneOf item 1 value
Type: string or number

root fcb_settings field010

deviceModeCfgEnable


Offset: 0x00000010, Width: 8b; [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable

root fcb_settings field010 oneOf item 0
Type: string or number
root fcb_settings field010 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field010 oneOf item 1 value
Type: string or number

root fcb_settings deviceModeType

deviceModeType


Offset: 0x00000011, Width: 8b; [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.

root fcb_settings deviceModeType oneOf item 0
Type: string or number
root fcb_settings deviceModeType oneOf item 1
Type: object
No Additional Properties

root fcb_settings deviceModeType oneOf item 1 value
Type: string or number

root fcb_settings field011

deviceModeType


Offset: 0x00000011, Width: 8b; [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.

root fcb_settings field011 oneOf item 0
Type: string or number
root fcb_settings field011 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field011 oneOf item 1 value
Type: string or number

root fcb_settings waitTimeCfgCommands

waitTimeCfgCommands


Offset: 0x00000012, Width: 16b; [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command

root fcb_settings waitTimeCfgCommands oneOf item 0
Type: string or number
root fcb_settings waitTimeCfgCommands oneOf item 1
Type: object
No Additional Properties

root fcb_settings waitTimeCfgCommands oneOf item 1 value
Type: string or number

root fcb_settings field012

waitTimeCfgCommands


Offset: 0x00000012, Width: 16b; [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command

root fcb_settings field012 oneOf item 0
Type: string or number
root fcb_settings field012 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field012 oneOf item 1 value
Type: string or number

root fcb_settings deviceModeSeq

deviceModeSeq


Offset: 0x00000014, Width: 32b; [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved

root fcb_settings deviceModeSeq oneOf item 0
Type: string or number
root fcb_settings deviceModeSeq oneOf item 1
Type: object
No Additional Properties

root fcb_settings deviceModeSeq oneOf item 1 value
Type: string or number
root fcb_settings deviceModeSeq oneOf item 2
Type: object
No Additional Properties

root fcb_settings deviceModeSeq oneOf item 2 bitfields
Type: object

root fcb_settings deviceModeSeq oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings deviceModeSeq oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings deviceModeSeq oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings deviceModeSeq oneOf item 3
Type: object
No Additional Properties

root fcb_settings deviceModeSeq oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings deviceModeSeq oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings deviceModeSeq oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field014

deviceModeSeq


Offset: 0x00000014, Width: 32b; [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved

root fcb_settings field014 oneOf item 0
Type: string or number
root fcb_settings field014 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field014 oneOf item 1 value
Type: string or number
root fcb_settings field014 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field014 oneOf item 2 bitfields
Type: object

root fcb_settings field014 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field014 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field014 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field014 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field014 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field014 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field014 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings deviceModeArg

deviceModeArg


Offset: 0x00000018, Width: 32b; [0x018-0x01b] Argument/Parameter for device configuration

root fcb_settings deviceModeArg oneOf item 0
Type: string or number
root fcb_settings deviceModeArg oneOf item 1
Type: object
No Additional Properties

root fcb_settings deviceModeArg oneOf item 1 value
Type: string or number

root fcb_settings field018

deviceModeArg


Offset: 0x00000018, Width: 32b; [0x018-0x01b] Argument/Parameter for device configuration

root fcb_settings field018 oneOf item 0
Type: string or number
root fcb_settings field018 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field018 oneOf item 1 value
Type: string or number

root fcb_settings configCmdEnable

configCmdEnable


Offset: 0x0000001C, Width: 8b; [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable

root fcb_settings configCmdEnable oneOf item 0
Type: string or number
root fcb_settings configCmdEnable oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdEnable oneOf item 1 value
Type: string or number

root fcb_settings field01C

configCmdEnable


Offset: 0x0000001C, Width: 8b; [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable

root fcb_settings field01C oneOf item 0
Type: string or number
root fcb_settings field01C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field01C oneOf item 1 value
Type: string or number

root fcb_settings configModeType_0

configModeType_0


Offset: 0x0000001D, Width: 8b; [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

root fcb_settings configModeType_0 oneOf item 0
Type: string or number
root fcb_settings configModeType_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configModeType_0 oneOf item 1 value
Type: string or number

root fcb_settings field01D

configModeType_0


Offset: 0x0000001D, Width: 8b; [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

root fcb_settings field01D oneOf item 0
Type: string or number
root fcb_settings field01D oneOf item 1
Type: object
No Additional Properties

root fcb_settings field01D oneOf item 1 value
Type: string or number

root fcb_settings configModeType_1

configModeType_1


Offset: 0x0000001E, Width: 8b; [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

root fcb_settings configModeType_1 oneOf item 0
Type: string or number
root fcb_settings configModeType_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configModeType_1 oneOf item 1 value
Type: string or number

root fcb_settings field01E

configModeType_1


Offset: 0x0000001E, Width: 8b; [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

root fcb_settings field01E oneOf item 0
Type: string or number
root fcb_settings field01E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field01E oneOf item 1 value
Type: string or number

root fcb_settings configModeType_2

configModeType_2


Offset: 0x0000001F, Width: 8b; [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

root fcb_settings configModeType_2 oneOf item 0
Type: string or number
root fcb_settings configModeType_2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configModeType_2 oneOf item 1 value
Type: string or number

root fcb_settings field01F

configModeType_2


Offset: 0x0000001F, Width: 8b; [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe

root fcb_settings field01F oneOf item 0
Type: string or number
root fcb_settings field01F oneOf item 1
Type: object
No Additional Properties

root fcb_settings field01F oneOf item 1 value
Type: string or number

root fcb_settings configCmdSeqs_0

configCmdSeqs_0


Offset: 0x00000020, Width: 32b; [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

root fcb_settings configCmdSeqs_0 oneOf item 0
Type: string or number
root fcb_settings configCmdSeqs_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_0 oneOf item 1 value
Type: string or number
root fcb_settings configCmdSeqs_0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_0 oneOf item 2 bitfields
Type: object

root fcb_settings configCmdSeqs_0 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings configCmdSeqs_0 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings configCmdSeqs_0 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings configCmdSeqs_0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_0 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings configCmdSeqs_0 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings configCmdSeqs_0 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field020

configCmdSeqs_0


Offset: 0x00000020, Width: 32b; [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

root fcb_settings field020 oneOf item 0
Type: string or number
root fcb_settings field020 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field020 oneOf item 1 value
Type: string or number
root fcb_settings field020 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field020 oneOf item 2 bitfields
Type: object

root fcb_settings field020 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field020 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field020 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field020 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field020 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field020 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field020 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings configCmdSeqs_1

configCmdSeqs_1


Offset: 0x00000024, Width: 32b; [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

root fcb_settings configCmdSeqs_1 oneOf item 0
Type: string or number
root fcb_settings configCmdSeqs_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_1 oneOf item 1 value
Type: string or number
root fcb_settings configCmdSeqs_1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_1 oneOf item 2 bitfields
Type: object

root fcb_settings configCmdSeqs_1 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings configCmdSeqs_1 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings configCmdSeqs_1 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings configCmdSeqs_1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_1 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings configCmdSeqs_1 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings configCmdSeqs_1 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field024

configCmdSeqs_1


Offset: 0x00000024, Width: 32b; [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

root fcb_settings field024 oneOf item 0
Type: string or number
root fcb_settings field024 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field024 oneOf item 1 value
Type: string or number
root fcb_settings field024 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field024 oneOf item 2 bitfields
Type: object

root fcb_settings field024 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field024 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field024 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field024 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field024 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field024 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field024 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings configCmdSeqs_2

configCmdSeqs_2


Offset: 0x00000028, Width: 32b; [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

root fcb_settings configCmdSeqs_2 oneOf item 0
Type: string or number
root fcb_settings configCmdSeqs_2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_2 oneOf item 1 value
Type: string or number
root fcb_settings configCmdSeqs_2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_2 oneOf item 2 bitfields
Type: object

root fcb_settings configCmdSeqs_2 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings configCmdSeqs_2 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings configCmdSeqs_2 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings configCmdSeqs_2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings configCmdSeqs_2 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings configCmdSeqs_2 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings configCmdSeqs_2 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field028

configCmdSeqs_2


Offset: 0x00000028, Width: 32b; [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq

root fcb_settings field028 oneOf item 0
Type: string or number
root fcb_settings field028 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field028 oneOf item 1 value
Type: string or number
root fcb_settings field028 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field028 oneOf item 2 bitfields
Type: object

root fcb_settings field028 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field028 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field028 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field028 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field028 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field028 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field028 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings reserved1

reserved1


Offset: 0x0000002C, Width: 32b; [0x02c-0x02f] Reserved for future use

root fcb_settings reserved1 oneOf item 0
Type: string or number
root fcb_settings reserved1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved1 oneOf item 1 value
Type: string or number

root fcb_settings field02C

reserved1


Offset: 0x0000002C, Width: 32b; [0x02c-0x02f] Reserved for future use

root fcb_settings field02C oneOf item 0
Type: string or number
root fcb_settings field02C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field02C oneOf item 1 value
Type: string or number

root fcb_settings configCmdArgs_0

configCmdArgs_0


Offset: 0x00000030, Width: 32b; [0x030-0x03b] Arguments/Parameters for device Configuration commands

root fcb_settings configCmdArgs_0 oneOf item 0
Type: string or number
root fcb_settings configCmdArgs_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdArgs_0 oneOf item 1 value
Type: string or number

root fcb_settings field030

configCmdArgs_0


Offset: 0x00000030, Width: 32b; [0x030-0x03b] Arguments/Parameters for device Configuration commands

root fcb_settings field030 oneOf item 0
Type: string or number
root fcb_settings field030 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field030 oneOf item 1 value
Type: string or number

root fcb_settings configCmdArgs_1

configCmdArgs_1


Offset: 0x00000034, Width: 32b; [0x030-0x03b] Arguments/Parameters for device Configuration commands

root fcb_settings configCmdArgs_1 oneOf item 0
Type: string or number
root fcb_settings configCmdArgs_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdArgs_1 oneOf item 1 value
Type: string or number

root fcb_settings field034

configCmdArgs_1


Offset: 0x00000034, Width: 32b; [0x030-0x03b] Arguments/Parameters for device Configuration commands

root fcb_settings field034 oneOf item 0
Type: string or number
root fcb_settings field034 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field034 oneOf item 1 value
Type: string or number

root fcb_settings configCmdArgs_2

configCmdArgs_2


Offset: 0x00000038, Width: 32b; [0x030-0x03b] Arguments/Parameters for device Configuration commands

root fcb_settings configCmdArgs_2 oneOf item 0
Type: string or number
root fcb_settings configCmdArgs_2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings configCmdArgs_2 oneOf item 1 value
Type: string or number

root fcb_settings field038

configCmdArgs_2


Offset: 0x00000038, Width: 32b; [0x030-0x03b] Arguments/Parameters for device Configuration commands

root fcb_settings field038 oneOf item 0
Type: string or number
root fcb_settings field038 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field038 oneOf item 1 value
Type: string or number

root fcb_settings reserved2

reserved2


Offset: 0x0000003C, Width: 32b; [0x03c-0x03f] Reserved for future use

root fcb_settings reserved2 oneOf item 0
Type: string or number
root fcb_settings reserved2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved2 oneOf item 1 value
Type: string or number

root fcb_settings field03C

reserved2


Offset: 0x0000003C, Width: 32b; [0x03c-0x03f] Reserved for future use

root fcb_settings field03C oneOf item 0
Type: string or number
root fcb_settings field03C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field03C oneOf item 1 value
Type: string or number

root fcb_settings controllerMiscOption

controllerMiscOption


Offset: 0x00000040, Width: 32b; [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details

root fcb_settings controllerMiscOption oneOf item 0
Type: string or number
root fcb_settings controllerMiscOption oneOf item 1
Type: object
No Additional Properties

root fcb_settings controllerMiscOption oneOf item 1 value
Type: string or number

root fcb_settings field040

controllerMiscOption


Offset: 0x00000040, Width: 32b; [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details

root fcb_settings field040 oneOf item 0
Type: string or number
root fcb_settings field040 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field040 oneOf item 1 value
Type: string or number

root fcb_settings deviceType

deviceType


Offset: 0x00000044, Width: 8b; [0x044-0x044] Device Type: See Flash Type Definition for more details

root fcb_settings deviceType oneOf item 0
Type: string or number
root fcb_settings deviceType oneOf item 1
Type: object
No Additional Properties

root fcb_settings deviceType oneOf item 1 value
Type: string or number

root fcb_settings field044

deviceType


Offset: 0x00000044, Width: 8b; [0x044-0x044] Device Type: See Flash Type Definition for more details

root fcb_settings field044 oneOf item 0
Type: string or number
root fcb_settings field044 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field044 oneOf item 1 value
Type: string or number

root fcb_settings sflashPadType

sflashPadType


Offset: 0x00000045, Width: 8b; [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal

root fcb_settings sflashPadType oneOf item 0
Type: string or number
root fcb_settings sflashPadType oneOf item 1
Type: object
No Additional Properties

root fcb_settings sflashPadType oneOf item 1 value
Type: string or number

root fcb_settings field045

sflashPadType


Offset: 0x00000045, Width: 8b; [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal

root fcb_settings field045 oneOf item 0
Type: string or number
root fcb_settings field045 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field045 oneOf item 1 value
Type: string or number

root fcb_settings serialClkFreq

serialClkFreq


Offset: 0x00000046, Width: 8b; [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details

root fcb_settings serialClkFreq oneOf item 0
Type: string or number
root fcb_settings serialClkFreq oneOf item 1
Type: object
No Additional Properties

root fcb_settings serialClkFreq oneOf item 1 value
Type: string or number

root fcb_settings field046

serialClkFreq


Offset: 0x00000046, Width: 8b; [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details

root fcb_settings field046 oneOf item 0
Type: string or number
root fcb_settings field046 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field046 oneOf item 1 value
Type: string or number

root fcb_settings lutCustomSeqEnable

lutCustomSeqEnable


Offset: 0x00000047, Width: 8b; [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH

root fcb_settings lutCustomSeqEnable oneOf item 0
Type: string or number
root fcb_settings lutCustomSeqEnable oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeqEnable oneOf item 1 value
Type: string or number

root fcb_settings field047

lutCustomSeqEnable


Offset: 0x00000047, Width: 8b; [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH

root fcb_settings field047 oneOf item 0
Type: string or number
root fcb_settings field047 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field047 oneOf item 1 value
Type: string or number

root fcb_settings reserved3_0

reserved3_0


Offset: 0x00000048, Width: 32b; [0x048-0x04f] Reserved for future use

root fcb_settings reserved3_0 oneOf item 0
Type: string or number
root fcb_settings reserved3_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved3_0 oneOf item 1 value
Type: string or number

root fcb_settings field048

reserved3_0


Offset: 0x00000048, Width: 32b; [0x048-0x04f] Reserved for future use

root fcb_settings field048 oneOf item 0
Type: string or number
root fcb_settings field048 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field048 oneOf item 1 value
Type: string or number

root fcb_settings reserved3_1

reserved3_1


Offset: 0x0000004C, Width: 32b; [0x048-0x04f] Reserved for future use

root fcb_settings reserved3_1 oneOf item 0
Type: string or number
root fcb_settings reserved3_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved3_1 oneOf item 1 value
Type: string or number

root fcb_settings field04C

reserved3_1


Offset: 0x0000004C, Width: 32b; [0x048-0x04f] Reserved for future use

root fcb_settings field04C oneOf item 0
Type: string or number
root fcb_settings field04C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field04C oneOf item 1 value
Type: string or number

root fcb_settings sflashA1Size

sflashA1Size


Offset: 0x00000050, Width: 32b; [0x050-0x053] Size of Flash connected to A1

root fcb_settings sflashA1Size oneOf item 0
Type: string or number
root fcb_settings sflashA1Size oneOf item 1
Type: object
No Additional Properties

root fcb_settings sflashA1Size oneOf item 1 value
Type: string or number

root fcb_settings field050

sflashA1Size


Offset: 0x00000050, Width: 32b; [0x050-0x053] Size of Flash connected to A1

root fcb_settings field050 oneOf item 0
Type: string or number
root fcb_settings field050 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field050 oneOf item 1 value
Type: string or number

root fcb_settings sflashA2Size

sflashA2Size


Offset: 0x00000054, Width: 32b; [0x054-0x057] Size of Flash connected to A2

root fcb_settings sflashA2Size oneOf item 0
Type: string or number
root fcb_settings sflashA2Size oneOf item 1
Type: object
No Additional Properties

root fcb_settings sflashA2Size oneOf item 1 value
Type: string or number

root fcb_settings field054

sflashA2Size


Offset: 0x00000054, Width: 32b; [0x054-0x057] Size of Flash connected to A2

root fcb_settings field054 oneOf item 0
Type: string or number
root fcb_settings field054 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field054 oneOf item 1 value
Type: string or number

root fcb_settings sflashB1Size

sflashB1Size


Offset: 0x00000058, Width: 32b; [0x058-0x05b] Size of Flash connected to B1

root fcb_settings sflashB1Size oneOf item 0
Type: string or number
root fcb_settings sflashB1Size oneOf item 1
Type: object
No Additional Properties

root fcb_settings sflashB1Size oneOf item 1 value
Type: string or number

root fcb_settings field058

sflashB1Size


Offset: 0x00000058, Width: 32b; [0x058-0x05b] Size of Flash connected to B1

root fcb_settings field058 oneOf item 0
Type: string or number
root fcb_settings field058 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field058 oneOf item 1 value
Type: string or number

root fcb_settings sflashB2Size

sflashB2Size


Offset: 0x0000005C, Width: 32b; [0x05c-0x05f] Size of Flash connected to B2

root fcb_settings sflashB2Size oneOf item 0
Type: string or number
root fcb_settings sflashB2Size oneOf item 1
Type: object
No Additional Properties

root fcb_settings sflashB2Size oneOf item 1 value
Type: string or number

root fcb_settings field05C

sflashB2Size


Offset: 0x0000005C, Width: 32b; [0x05c-0x05f] Size of Flash connected to B2

root fcb_settings field05C oneOf item 0
Type: string or number
root fcb_settings field05C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field05C oneOf item 1 value
Type: string or number

root fcb_settings csPadSettingOverride

csPadSettingOverride


Offset: 0x00000060, Width: 32b; [0x060-0x063] CS pad setting override value

root fcb_settings csPadSettingOverride oneOf item 0
Type: string or number
root fcb_settings csPadSettingOverride oneOf item 1
Type: object
No Additional Properties

root fcb_settings csPadSettingOverride oneOf item 1 value
Type: string or number

root fcb_settings field060

csPadSettingOverride


Offset: 0x00000060, Width: 32b; [0x060-0x063] CS pad setting override value

root fcb_settings field060 oneOf item 0
Type: string or number
root fcb_settings field060 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field060 oneOf item 1 value
Type: string or number

root fcb_settings sclkPadSettingOverride

sclkPadSettingOverride


Offset: 0x00000064, Width: 32b; [0x064-0x067] SCK pad setting override value

root fcb_settings sclkPadSettingOverride oneOf item 0
Type: string or number
root fcb_settings sclkPadSettingOverride oneOf item 1
Type: object
No Additional Properties

root fcb_settings field064

sclkPadSettingOverride


Offset: 0x00000064, Width: 32b; [0x064-0x067] SCK pad setting override value

root fcb_settings field064 oneOf item 0
Type: string or number
root fcb_settings field064 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field064 oneOf item 1 value
Type: string or number

root fcb_settings dataPadSettingOverride

dataPadSettingOverride


Offset: 0x00000068, Width: 32b; [0x068-0x06b] data pad setting override value

root fcb_settings dataPadSettingOverride oneOf item 0
Type: string or number
root fcb_settings dataPadSettingOverride oneOf item 1
Type: object
No Additional Properties

root fcb_settings field068

dataPadSettingOverride


Offset: 0x00000068, Width: 32b; [0x068-0x06b] data pad setting override value

root fcb_settings field068 oneOf item 0
Type: string or number
root fcb_settings field068 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field068 oneOf item 1 value
Type: string or number

root fcb_settings dqsPadSettingOverride

dqsPadSettingOverride


Offset: 0x0000006C, Width: 32b; [0x06c-0x06f] DQS pad setting override value

root fcb_settings dqsPadSettingOverride oneOf item 0
Type: string or number
root fcb_settings dqsPadSettingOverride oneOf item 1
Type: object
No Additional Properties

root fcb_settings dqsPadSettingOverride oneOf item 1 value
Type: string or number

root fcb_settings field06C

dqsPadSettingOverride


Offset: 0x0000006C, Width: 32b; [0x06c-0x06f] DQS pad setting override value

root fcb_settings field06C oneOf item 0
Type: string or number
root fcb_settings field06C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field06C oneOf item 1 value
Type: string or number

root fcb_settings timeoutInMs

timeoutInMs


Offset: 0x00000070, Width: 32b; [0x070-0x073] Timeout threshold for read status command

root fcb_settings timeoutInMs oneOf item 0
Type: string or number
root fcb_settings timeoutInMs oneOf item 1
Type: object
No Additional Properties

root fcb_settings timeoutInMs oneOf item 1 value
Type: string or number

root fcb_settings field070

timeoutInMs


Offset: 0x00000070, Width: 32b; [0x070-0x073] Timeout threshold for read status command

root fcb_settings field070 oneOf item 0
Type: string or number
root fcb_settings field070 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field070 oneOf item 1 value
Type: string or number

root fcb_settings commandInterval

commandInterval


Offset: 0x00000074, Width: 32b; [0x074-0x077] CS deselect interval between two commands

root fcb_settings commandInterval oneOf item 0
Type: string or number
root fcb_settings commandInterval oneOf item 1
Type: object
No Additional Properties

root fcb_settings commandInterval oneOf item 1 value
Type: string or number

root fcb_settings field074

commandInterval


Offset: 0x00000074, Width: 32b; [0x074-0x077] CS deselect interval between two commands

root fcb_settings field074 oneOf item 0
Type: string or number
root fcb_settings field074 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field074 oneOf item 1 value
Type: string or number

root fcb_settings dataValidTime_0

dataValidTime_0


Offset: 0x00000078, Width: 16b; [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B

root fcb_settings dataValidTime_0 oneOf item 0
Type: string or number
root fcb_settings dataValidTime_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings dataValidTime_0 oneOf item 1 value
Type: string or number

root fcb_settings field078

dataValidTime_0


Offset: 0x00000078, Width: 16b; [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B

root fcb_settings field078 oneOf item 0
Type: string or number
root fcb_settings field078 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field078 oneOf item 1 value
Type: string or number

root fcb_settings dataValidTime_1

dataValidTime_1


Offset: 0x0000007A, Width: 16b; [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B

root fcb_settings dataValidTime_1 oneOf item 0
Type: string or number
root fcb_settings dataValidTime_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings dataValidTime_1 oneOf item 1 value
Type: string or number

root fcb_settings field07A

dataValidTime_1


Offset: 0x0000007A, Width: 16b; [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B

root fcb_settings field07A oneOf item 0
Type: string or number
root fcb_settings field07A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field07A oneOf item 1 value
Type: string or number

root fcb_settings busyOffset

busyOffset


Offset: 0x0000007C, Width: 16b; [0x07c-0x07d] Busy offset, valid value: 0-31

root fcb_settings busyOffset oneOf item 0
Type: string or number
root fcb_settings busyOffset oneOf item 1
Type: object
No Additional Properties

root fcb_settings busyOffset oneOf item 1 value
Type: string or number

root fcb_settings field07C

busyOffset


Offset: 0x0000007C, Width: 16b; [0x07c-0x07d] Busy offset, valid value: 0-31

root fcb_settings field07C oneOf item 0
Type: string or number
root fcb_settings field07C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field07C oneOf item 1 value
Type: string or number

root fcb_settings busyBitPolarity

busyBitPolarity


Offset: 0x0000007E, Width: 16b; [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy

root fcb_settings busyBitPolarity oneOf item 0
Type: string or number
root fcb_settings busyBitPolarity oneOf item 1
Type: object
No Additional Properties

root fcb_settings busyBitPolarity oneOf item 1 value
Type: string or number

root fcb_settings field07E

busyBitPolarity


Offset: 0x0000007E, Width: 16b; [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy

root fcb_settings field07E oneOf item 0
Type: string or number
root fcb_settings field07E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field07E oneOf item 1 value
Type: string or number

root fcb_settings lookupTable_seq0_instr0

lookupTable_seq0_instr0


Offset: 0x00000080, Width: 16b; Lookup table holds Flash command sequences 0, instruction 0

root fcb_settings lookupTable_seq0_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field080

lookupTable_seq0_instr0


Offset: 0x00000080, Width: 16b; Lookup table holds Flash command sequences 0, instruction 0

root fcb_settings field080 oneOf item 0
Type: string or number
root fcb_settings field080 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field080 oneOf item 1 value
Type: string or number
root fcb_settings field080 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field080 oneOf item 2 bitfields
Type: object

root fcb_settings field080 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field080 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field080 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field080 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field080 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field080 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field080 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr1

lookupTable_seq0_instr1


Offset: 0x00000082, Width: 16b; Lookup table holds Flash command sequences 0, instruction 1

root fcb_settings lookupTable_seq0_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field082

lookupTable_seq0_instr1


Offset: 0x00000082, Width: 16b; Lookup table holds Flash command sequences 0, instruction 1

root fcb_settings field082 oneOf item 0
Type: string or number
root fcb_settings field082 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field082 oneOf item 1 value
Type: string or number
root fcb_settings field082 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field082 oneOf item 2 bitfields
Type: object

root fcb_settings field082 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field082 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field082 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field082 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field082 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field082 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field082 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr2

lookupTable_seq0_instr2


Offset: 0x00000084, Width: 16b; Lookup table holds Flash command sequences 0, instruction 2

root fcb_settings lookupTable_seq0_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field084

lookupTable_seq0_instr2


Offset: 0x00000084, Width: 16b; Lookup table holds Flash command sequences 0, instruction 2

root fcb_settings field084 oneOf item 0
Type: string or number
root fcb_settings field084 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field084 oneOf item 1 value
Type: string or number
root fcb_settings field084 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field084 oneOf item 2 bitfields
Type: object

root fcb_settings field084 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field084 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field084 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field084 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field084 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field084 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field084 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr3

lookupTable_seq0_instr3


Offset: 0x00000086, Width: 16b; Lookup table holds Flash command sequences 0, instruction 3

root fcb_settings lookupTable_seq0_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field086

lookupTable_seq0_instr3


Offset: 0x00000086, Width: 16b; Lookup table holds Flash command sequences 0, instruction 3

root fcb_settings field086 oneOf item 0
Type: string or number
root fcb_settings field086 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field086 oneOf item 1 value
Type: string or number
root fcb_settings field086 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field086 oneOf item 2 bitfields
Type: object

root fcb_settings field086 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field086 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field086 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field086 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field086 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field086 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field086 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr4

lookupTable_seq0_instr4


Offset: 0x00000088, Width: 16b; Lookup table holds Flash command sequences 0, instruction 4

root fcb_settings lookupTable_seq0_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field088

lookupTable_seq0_instr4


Offset: 0x00000088, Width: 16b; Lookup table holds Flash command sequences 0, instruction 4

root fcb_settings field088 oneOf item 0
Type: string or number
root fcb_settings field088 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field088 oneOf item 1 value
Type: string or number
root fcb_settings field088 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field088 oneOf item 2 bitfields
Type: object

root fcb_settings field088 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field088 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field088 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field088 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field088 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field088 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field088 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr5

lookupTable_seq0_instr5


Offset: 0x0000008A, Width: 16b; Lookup table holds Flash command sequences 0, instruction 5

root fcb_settings lookupTable_seq0_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field08A

lookupTable_seq0_instr5


Offset: 0x0000008A, Width: 16b; Lookup table holds Flash command sequences 0, instruction 5

root fcb_settings field08A oneOf item 0
Type: string or number
root fcb_settings field08A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field08A oneOf item 1 value
Type: string or number
root fcb_settings field08A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field08A oneOf item 2 bitfields
Type: object

root fcb_settings field08A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field08A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field08A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field08A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field08A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field08A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field08A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr6

lookupTable_seq0_instr6


Offset: 0x0000008C, Width: 16b; Lookup table holds Flash command sequences 0, instruction 6

root fcb_settings lookupTable_seq0_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field08C

lookupTable_seq0_instr6


Offset: 0x0000008C, Width: 16b; Lookup table holds Flash command sequences 0, instruction 6

root fcb_settings field08C oneOf item 0
Type: string or number
root fcb_settings field08C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field08C oneOf item 1 value
Type: string or number
root fcb_settings field08C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field08C oneOf item 2 bitfields
Type: object

root fcb_settings field08C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field08C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field08C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field08C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field08C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field08C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field08C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr7

lookupTable_seq0_instr7


Offset: 0x0000008E, Width: 16b; Lookup table holds Flash command sequences 0, instruction 7

root fcb_settings lookupTable_seq0_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq0_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq0_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq0_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq0_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq0_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq0_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field08E

lookupTable_seq0_instr7


Offset: 0x0000008E, Width: 16b; Lookup table holds Flash command sequences 0, instruction 7

root fcb_settings field08E oneOf item 0
Type: string or number
root fcb_settings field08E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field08E oneOf item 1 value
Type: string or number
root fcb_settings field08E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field08E oneOf item 2 bitfields
Type: object

root fcb_settings field08E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field08E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field08E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field08E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field08E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field08E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field08E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr0

lookupTable_seq1_instr0


Offset: 0x00000090, Width: 16b; Lookup table holds Flash command sequences 1, instruction 0

root fcb_settings lookupTable_seq1_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field090

lookupTable_seq1_instr0


Offset: 0x00000090, Width: 16b; Lookup table holds Flash command sequences 1, instruction 0

root fcb_settings field090 oneOf item 0
Type: string or number
root fcb_settings field090 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field090 oneOf item 1 value
Type: string or number
root fcb_settings field090 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field090 oneOf item 2 bitfields
Type: object

root fcb_settings field090 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field090 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field090 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field090 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field090 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field090 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field090 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr1

lookupTable_seq1_instr1


Offset: 0x00000092, Width: 16b; Lookup table holds Flash command sequences 1, instruction 1

root fcb_settings lookupTable_seq1_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field092

lookupTable_seq1_instr1


Offset: 0x00000092, Width: 16b; Lookup table holds Flash command sequences 1, instruction 1

root fcb_settings field092 oneOf item 0
Type: string or number
root fcb_settings field092 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field092 oneOf item 1 value
Type: string or number
root fcb_settings field092 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field092 oneOf item 2 bitfields
Type: object

root fcb_settings field092 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field092 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field092 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field092 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field092 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field092 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field092 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr2

lookupTable_seq1_instr2


Offset: 0x00000094, Width: 16b; Lookup table holds Flash command sequences 1, instruction 2

root fcb_settings lookupTable_seq1_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field094

lookupTable_seq1_instr2


Offset: 0x00000094, Width: 16b; Lookup table holds Flash command sequences 1, instruction 2

root fcb_settings field094 oneOf item 0
Type: string or number
root fcb_settings field094 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field094 oneOf item 1 value
Type: string or number
root fcb_settings field094 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field094 oneOf item 2 bitfields
Type: object

root fcb_settings field094 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field094 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field094 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field094 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field094 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field094 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field094 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr3

lookupTable_seq1_instr3


Offset: 0x00000096, Width: 16b; Lookup table holds Flash command sequences 1, instruction 3

root fcb_settings lookupTable_seq1_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field096

lookupTable_seq1_instr3


Offset: 0x00000096, Width: 16b; Lookup table holds Flash command sequences 1, instruction 3

root fcb_settings field096 oneOf item 0
Type: string or number
root fcb_settings field096 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field096 oneOf item 1 value
Type: string or number
root fcb_settings field096 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field096 oneOf item 2 bitfields
Type: object

root fcb_settings field096 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field096 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field096 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field096 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field096 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field096 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field096 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr4

lookupTable_seq1_instr4


Offset: 0x00000098, Width: 16b; Lookup table holds Flash command sequences 1, instruction 4

root fcb_settings lookupTable_seq1_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field098

lookupTable_seq1_instr4


Offset: 0x00000098, Width: 16b; Lookup table holds Flash command sequences 1, instruction 4

root fcb_settings field098 oneOf item 0
Type: string or number
root fcb_settings field098 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field098 oneOf item 1 value
Type: string or number
root fcb_settings field098 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field098 oneOf item 2 bitfields
Type: object

root fcb_settings field098 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field098 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field098 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field098 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field098 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field098 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field098 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr5

lookupTable_seq1_instr5


Offset: 0x0000009A, Width: 16b; Lookup table holds Flash command sequences 1, instruction 5

root fcb_settings lookupTable_seq1_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field09A

lookupTable_seq1_instr5


Offset: 0x0000009A, Width: 16b; Lookup table holds Flash command sequences 1, instruction 5

root fcb_settings field09A oneOf item 0
Type: string or number
root fcb_settings field09A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field09A oneOf item 1 value
Type: string or number
root fcb_settings field09A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field09A oneOf item 2 bitfields
Type: object

root fcb_settings field09A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field09A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field09A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field09A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field09A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field09A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field09A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr6

lookupTable_seq1_instr6


Offset: 0x0000009C, Width: 16b; Lookup table holds Flash command sequences 1, instruction 6

root fcb_settings lookupTable_seq1_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field09C

lookupTable_seq1_instr6


Offset: 0x0000009C, Width: 16b; Lookup table holds Flash command sequences 1, instruction 6

root fcb_settings field09C oneOf item 0
Type: string or number
root fcb_settings field09C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field09C oneOf item 1 value
Type: string or number
root fcb_settings field09C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field09C oneOf item 2 bitfields
Type: object

root fcb_settings field09C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field09C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field09C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field09C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field09C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field09C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field09C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr7

lookupTable_seq1_instr7


Offset: 0x0000009E, Width: 16b; Lookup table holds Flash command sequences 1, instruction 7

root fcb_settings lookupTable_seq1_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq1_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq1_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq1_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq1_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq1_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq1_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field09E

lookupTable_seq1_instr7


Offset: 0x0000009E, Width: 16b; Lookup table holds Flash command sequences 1, instruction 7

root fcb_settings field09E oneOf item 0
Type: string or number
root fcb_settings field09E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field09E oneOf item 1 value
Type: string or number
root fcb_settings field09E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field09E oneOf item 2 bitfields
Type: object

root fcb_settings field09E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field09E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field09E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field09E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field09E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field09E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field09E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr0

lookupTable_seq2_instr0


Offset: 0x000000A0, Width: 16b; Lookup table holds Flash command sequences 2, instruction 0

root fcb_settings lookupTable_seq2_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A0

lookupTable_seq2_instr0


Offset: 0x000000A0, Width: 16b; Lookup table holds Flash command sequences 2, instruction 0

root fcb_settings field0A0 oneOf item 0
Type: string or number
root fcb_settings field0A0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0A0 oneOf item 1 value
Type: string or number
root fcb_settings field0A0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0A0 oneOf item 2 bitfields
Type: object

root fcb_settings field0A0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0A0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr1

lookupTable_seq2_instr1


Offset: 0x000000A2, Width: 16b; Lookup table holds Flash command sequences 2, instruction 1

root fcb_settings lookupTable_seq2_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A2

lookupTable_seq2_instr1


Offset: 0x000000A2, Width: 16b; Lookup table holds Flash command sequences 2, instruction 1

root fcb_settings field0A2 oneOf item 0
Type: string or number
root fcb_settings field0A2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0A2 oneOf item 1 value
Type: string or number
root fcb_settings field0A2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0A2 oneOf item 2 bitfields
Type: object

root fcb_settings field0A2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0A2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr2

lookupTable_seq2_instr2


Offset: 0x000000A4, Width: 16b; Lookup table holds Flash command sequences 2, instruction 2

root fcb_settings lookupTable_seq2_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A4

lookupTable_seq2_instr2


Offset: 0x000000A4, Width: 16b; Lookup table holds Flash command sequences 2, instruction 2

root fcb_settings field0A4 oneOf item 0
Type: string or number
root fcb_settings field0A4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0A4 oneOf item 1 value
Type: string or number
root fcb_settings field0A4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0A4 oneOf item 2 bitfields
Type: object

root fcb_settings field0A4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0A4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr3

lookupTable_seq2_instr3


Offset: 0x000000A6, Width: 16b; Lookup table holds Flash command sequences 2, instruction 3

root fcb_settings lookupTable_seq2_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A6

lookupTable_seq2_instr3


Offset: 0x000000A6, Width: 16b; Lookup table holds Flash command sequences 2, instruction 3

root fcb_settings field0A6 oneOf item 0
Type: string or number
root fcb_settings field0A6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0A6 oneOf item 1 value
Type: string or number
root fcb_settings field0A6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0A6 oneOf item 2 bitfields
Type: object

root fcb_settings field0A6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0A6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr4

lookupTable_seq2_instr4


Offset: 0x000000A8, Width: 16b; Lookup table holds Flash command sequences 2, instruction 4

root fcb_settings lookupTable_seq2_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A8

lookupTable_seq2_instr4


Offset: 0x000000A8, Width: 16b; Lookup table holds Flash command sequences 2, instruction 4

root fcb_settings field0A8 oneOf item 0
Type: string or number
root fcb_settings field0A8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0A8 oneOf item 1 value
Type: string or number
root fcb_settings field0A8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0A8 oneOf item 2 bitfields
Type: object

root fcb_settings field0A8 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A8 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A8 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0A8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0A8 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0A8 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0A8 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr5

lookupTable_seq2_instr5


Offset: 0x000000AA, Width: 16b; Lookup table holds Flash command sequences 2, instruction 5

root fcb_settings lookupTable_seq2_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0AA

lookupTable_seq2_instr5


Offset: 0x000000AA, Width: 16b; Lookup table holds Flash command sequences 2, instruction 5

root fcb_settings field0AA oneOf item 0
Type: string or number
root fcb_settings field0AA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0AA oneOf item 1 value
Type: string or number
root fcb_settings field0AA oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0AA oneOf item 2 bitfields
Type: object

root fcb_settings field0AA oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0AA oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0AA oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0AA oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0AA oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0AA oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0AA oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr6

lookupTable_seq2_instr6


Offset: 0x000000AC, Width: 16b; Lookup table holds Flash command sequences 2, instruction 6

root fcb_settings lookupTable_seq2_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0AC

lookupTable_seq2_instr6


Offset: 0x000000AC, Width: 16b; Lookup table holds Flash command sequences 2, instruction 6

root fcb_settings field0AC oneOf item 0
Type: string or number
root fcb_settings field0AC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0AC oneOf item 1 value
Type: string or number
root fcb_settings field0AC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0AC oneOf item 2 bitfields
Type: object

root fcb_settings field0AC oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0AC oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0AC oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0AC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0AC oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0AC oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0AC oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr7

lookupTable_seq2_instr7


Offset: 0x000000AE, Width: 16b; Lookup table holds Flash command sequences 2, instruction 7

root fcb_settings lookupTable_seq2_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq2_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq2_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq2_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq2_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq2_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq2_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0AE

lookupTable_seq2_instr7


Offset: 0x000000AE, Width: 16b; Lookup table holds Flash command sequences 2, instruction 7

root fcb_settings field0AE oneOf item 0
Type: string or number
root fcb_settings field0AE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0AE oneOf item 1 value
Type: string or number
root fcb_settings field0AE oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0AE oneOf item 2 bitfields
Type: object

root fcb_settings field0AE oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0AE oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0AE oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0AE oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0AE oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0AE oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0AE oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr0

lookupTable_seq3_instr0


Offset: 0x000000B0, Width: 16b; Lookup table holds Flash command sequences 3, instruction 0

root fcb_settings lookupTable_seq3_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B0

lookupTable_seq3_instr0


Offset: 0x000000B0, Width: 16b; Lookup table holds Flash command sequences 3, instruction 0

root fcb_settings field0B0 oneOf item 0
Type: string or number
root fcb_settings field0B0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0B0 oneOf item 1 value
Type: string or number
root fcb_settings field0B0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0B0 oneOf item 2 bitfields
Type: object

root fcb_settings field0B0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0B0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr1

lookupTable_seq3_instr1


Offset: 0x000000B2, Width: 16b; Lookup table holds Flash command sequences 3, instruction 1

root fcb_settings lookupTable_seq3_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B2

lookupTable_seq3_instr1


Offset: 0x000000B2, Width: 16b; Lookup table holds Flash command sequences 3, instruction 1

root fcb_settings field0B2 oneOf item 0
Type: string or number
root fcb_settings field0B2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0B2 oneOf item 1 value
Type: string or number
root fcb_settings field0B2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0B2 oneOf item 2 bitfields
Type: object

root fcb_settings field0B2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0B2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr2

lookupTable_seq3_instr2


Offset: 0x000000B4, Width: 16b; Lookup table holds Flash command sequences 3, instruction 2

root fcb_settings lookupTable_seq3_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B4

lookupTable_seq3_instr2


Offset: 0x000000B4, Width: 16b; Lookup table holds Flash command sequences 3, instruction 2

root fcb_settings field0B4 oneOf item 0
Type: string or number
root fcb_settings field0B4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0B4 oneOf item 1 value
Type: string or number
root fcb_settings field0B4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0B4 oneOf item 2 bitfields
Type: object

root fcb_settings field0B4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0B4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr3

lookupTable_seq3_instr3


Offset: 0x000000B6, Width: 16b; Lookup table holds Flash command sequences 3, instruction 3

root fcb_settings lookupTable_seq3_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B6

lookupTable_seq3_instr3


Offset: 0x000000B6, Width: 16b; Lookup table holds Flash command sequences 3, instruction 3

root fcb_settings field0B6 oneOf item 0
Type: string or number
root fcb_settings field0B6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0B6 oneOf item 1 value
Type: string or number
root fcb_settings field0B6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0B6 oneOf item 2 bitfields
Type: object

root fcb_settings field0B6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0B6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr4

lookupTable_seq3_instr4


Offset: 0x000000B8, Width: 16b; Lookup table holds Flash command sequences 3, instruction 4

root fcb_settings lookupTable_seq3_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B8

lookupTable_seq3_instr4


Offset: 0x000000B8, Width: 16b; Lookup table holds Flash command sequences 3, instruction 4

root fcb_settings field0B8 oneOf item 0
Type: string or number
root fcb_settings field0B8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0B8 oneOf item 1 value
Type: string or number
root fcb_settings field0B8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0B8 oneOf item 2 bitfields
Type: object

root fcb_settings field0B8 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B8 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B8 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0B8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0B8 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0B8 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0B8 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr5

lookupTable_seq3_instr5


Offset: 0x000000BA, Width: 16b; Lookup table holds Flash command sequences 3, instruction 5

root fcb_settings lookupTable_seq3_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0BA

lookupTable_seq3_instr5


Offset: 0x000000BA, Width: 16b; Lookup table holds Flash command sequences 3, instruction 5

root fcb_settings field0BA oneOf item 0
Type: string or number
root fcb_settings field0BA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0BA oneOf item 1 value
Type: string or number
root fcb_settings field0BA oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0BA oneOf item 2 bitfields
Type: object

root fcb_settings field0BA oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0BA oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0BA oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0BA oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0BA oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0BA oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0BA oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr6

lookupTable_seq3_instr6


Offset: 0x000000BC, Width: 16b; Lookup table holds Flash command sequences 3, instruction 6

root fcb_settings lookupTable_seq3_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0BC

lookupTable_seq3_instr6


Offset: 0x000000BC, Width: 16b; Lookup table holds Flash command sequences 3, instruction 6

root fcb_settings field0BC oneOf item 0
Type: string or number
root fcb_settings field0BC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0BC oneOf item 1 value
Type: string or number
root fcb_settings field0BC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0BC oneOf item 2 bitfields
Type: object

root fcb_settings field0BC oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0BC oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0BC oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0BC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0BC oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0BC oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0BC oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr7

lookupTable_seq3_instr7


Offset: 0x000000BE, Width: 16b; Lookup table holds Flash command sequences 3, instruction 7

root fcb_settings lookupTable_seq3_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq3_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq3_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq3_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq3_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq3_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq3_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0BE

lookupTable_seq3_instr7


Offset: 0x000000BE, Width: 16b; Lookup table holds Flash command sequences 3, instruction 7

root fcb_settings field0BE oneOf item 0
Type: string or number
root fcb_settings field0BE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0BE oneOf item 1 value
Type: string or number
root fcb_settings field0BE oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0BE oneOf item 2 bitfields
Type: object

root fcb_settings field0BE oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0BE oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0BE oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0BE oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0BE oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0BE oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0BE oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr0

lookupTable_seq4_instr0


Offset: 0x000000C0, Width: 16b; Lookup table holds Flash command sequences 4, instruction 0

root fcb_settings lookupTable_seq4_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C0

lookupTable_seq4_instr0


Offset: 0x000000C0, Width: 16b; Lookup table holds Flash command sequences 4, instruction 0

root fcb_settings field0C0 oneOf item 0
Type: string or number
root fcb_settings field0C0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0C0 oneOf item 1 value
Type: string or number
root fcb_settings field0C0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0C0 oneOf item 2 bitfields
Type: object

root fcb_settings field0C0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0C0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr1

lookupTable_seq4_instr1


Offset: 0x000000C2, Width: 16b; Lookup table holds Flash command sequences 4, instruction 1

root fcb_settings lookupTable_seq4_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C2

lookupTable_seq4_instr1


Offset: 0x000000C2, Width: 16b; Lookup table holds Flash command sequences 4, instruction 1

root fcb_settings field0C2 oneOf item 0
Type: string or number
root fcb_settings field0C2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0C2 oneOf item 1 value
Type: string or number
root fcb_settings field0C2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0C2 oneOf item 2 bitfields
Type: object

root fcb_settings field0C2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0C2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr2

lookupTable_seq4_instr2


Offset: 0x000000C4, Width: 16b; Lookup table holds Flash command sequences 4, instruction 2

root fcb_settings lookupTable_seq4_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C4

lookupTable_seq4_instr2


Offset: 0x000000C4, Width: 16b; Lookup table holds Flash command sequences 4, instruction 2

root fcb_settings field0C4 oneOf item 0
Type: string or number
root fcb_settings field0C4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0C4 oneOf item 1 value
Type: string or number
root fcb_settings field0C4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0C4 oneOf item 2 bitfields
Type: object

root fcb_settings field0C4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0C4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr3

lookupTable_seq4_instr3


Offset: 0x000000C6, Width: 16b; Lookup table holds Flash command sequences 4, instruction 3

root fcb_settings lookupTable_seq4_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C6

lookupTable_seq4_instr3


Offset: 0x000000C6, Width: 16b; Lookup table holds Flash command sequences 4, instruction 3

root fcb_settings field0C6 oneOf item 0
Type: string or number
root fcb_settings field0C6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0C6 oneOf item 1 value
Type: string or number
root fcb_settings field0C6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0C6 oneOf item 2 bitfields
Type: object

root fcb_settings field0C6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0C6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr4

lookupTable_seq4_instr4


Offset: 0x000000C8, Width: 16b; Lookup table holds Flash command sequences 4, instruction 4

root fcb_settings lookupTable_seq4_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C8

lookupTable_seq4_instr4


Offset: 0x000000C8, Width: 16b; Lookup table holds Flash command sequences 4, instruction 4

root fcb_settings field0C8 oneOf item 0
Type: string or number
root fcb_settings field0C8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0C8 oneOf item 1 value
Type: string or number
root fcb_settings field0C8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0C8 oneOf item 2 bitfields
Type: object

root fcb_settings field0C8 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C8 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C8 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0C8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0C8 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0C8 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0C8 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr5

lookupTable_seq4_instr5


Offset: 0x000000CA, Width: 16b; Lookup table holds Flash command sequences 4, instruction 5

root fcb_settings lookupTable_seq4_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0CA

lookupTable_seq4_instr5


Offset: 0x000000CA, Width: 16b; Lookup table holds Flash command sequences 4, instruction 5

root fcb_settings field0CA oneOf item 0
Type: string or number
root fcb_settings field0CA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0CA oneOf item 1 value
Type: string or number
root fcb_settings field0CA oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0CA oneOf item 2 bitfields
Type: object

root fcb_settings field0CA oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0CA oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0CA oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0CA oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0CA oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0CA oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0CA oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr6

lookupTable_seq4_instr6


Offset: 0x000000CC, Width: 16b; Lookup table holds Flash command sequences 4, instruction 6

root fcb_settings lookupTable_seq4_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0CC

lookupTable_seq4_instr6


Offset: 0x000000CC, Width: 16b; Lookup table holds Flash command sequences 4, instruction 6

root fcb_settings field0CC oneOf item 0
Type: string or number
root fcb_settings field0CC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0CC oneOf item 1 value
Type: string or number
root fcb_settings field0CC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0CC oneOf item 2 bitfields
Type: object

root fcb_settings field0CC oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0CC oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0CC oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0CC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0CC oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0CC oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0CC oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr7

lookupTable_seq4_instr7


Offset: 0x000000CE, Width: 16b; Lookup table holds Flash command sequences 4, instruction 7

root fcb_settings lookupTable_seq4_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq4_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq4_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq4_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq4_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq4_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq4_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0CE

lookupTable_seq4_instr7


Offset: 0x000000CE, Width: 16b; Lookup table holds Flash command sequences 4, instruction 7

root fcb_settings field0CE oneOf item 0
Type: string or number
root fcb_settings field0CE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0CE oneOf item 1 value
Type: string or number
root fcb_settings field0CE oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0CE oneOf item 2 bitfields
Type: object

root fcb_settings field0CE oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0CE oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0CE oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0CE oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0CE oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0CE oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0CE oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr0

lookupTable_seq5_instr0


Offset: 0x000000D0, Width: 16b; Lookup table holds Flash command sequences 5, instruction 0

root fcb_settings lookupTable_seq5_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D0

lookupTable_seq5_instr0


Offset: 0x000000D0, Width: 16b; Lookup table holds Flash command sequences 5, instruction 0

root fcb_settings field0D0 oneOf item 0
Type: string or number
root fcb_settings field0D0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0D0 oneOf item 1 value
Type: string or number
root fcb_settings field0D0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0D0 oneOf item 2 bitfields
Type: object

root fcb_settings field0D0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0D0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr1

lookupTable_seq5_instr1


Offset: 0x000000D2, Width: 16b; Lookup table holds Flash command sequences 5, instruction 1

root fcb_settings lookupTable_seq5_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D2

lookupTable_seq5_instr1


Offset: 0x000000D2, Width: 16b; Lookup table holds Flash command sequences 5, instruction 1

root fcb_settings field0D2 oneOf item 0
Type: string or number
root fcb_settings field0D2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0D2 oneOf item 1 value
Type: string or number
root fcb_settings field0D2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0D2 oneOf item 2 bitfields
Type: object

root fcb_settings field0D2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0D2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr2

lookupTable_seq5_instr2


Offset: 0x000000D4, Width: 16b; Lookup table holds Flash command sequences 5, instruction 2

root fcb_settings lookupTable_seq5_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D4

lookupTable_seq5_instr2


Offset: 0x000000D4, Width: 16b; Lookup table holds Flash command sequences 5, instruction 2

root fcb_settings field0D4 oneOf item 0
Type: string or number
root fcb_settings field0D4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0D4 oneOf item 1 value
Type: string or number
root fcb_settings field0D4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0D4 oneOf item 2 bitfields
Type: object

root fcb_settings field0D4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0D4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr3

lookupTable_seq5_instr3


Offset: 0x000000D6, Width: 16b; Lookup table holds Flash command sequences 5, instruction 3

root fcb_settings lookupTable_seq5_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D6

lookupTable_seq5_instr3


Offset: 0x000000D6, Width: 16b; Lookup table holds Flash command sequences 5, instruction 3

root fcb_settings field0D6 oneOf item 0
Type: string or number
root fcb_settings field0D6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0D6 oneOf item 1 value
Type: string or number
root fcb_settings field0D6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0D6 oneOf item 2 bitfields
Type: object

root fcb_settings field0D6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0D6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr4

lookupTable_seq5_instr4


Offset: 0x000000D8, Width: 16b; Lookup table holds Flash command sequences 5, instruction 4

root fcb_settings lookupTable_seq5_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D8

lookupTable_seq5_instr4


Offset: 0x000000D8, Width: 16b; Lookup table holds Flash command sequences 5, instruction 4

root fcb_settings field0D8 oneOf item 0
Type: string or number
root fcb_settings field0D8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0D8 oneOf item 1 value
Type: string or number
root fcb_settings field0D8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0D8 oneOf item 2 bitfields
Type: object

root fcb_settings field0D8 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D8 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D8 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0D8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0D8 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0D8 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0D8 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr5

lookupTable_seq5_instr5


Offset: 0x000000DA, Width: 16b; Lookup table holds Flash command sequences 5, instruction 5

root fcb_settings lookupTable_seq5_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0DA

lookupTable_seq5_instr5


Offset: 0x000000DA, Width: 16b; Lookup table holds Flash command sequences 5, instruction 5

root fcb_settings field0DA oneOf item 0
Type: string or number
root fcb_settings field0DA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0DA oneOf item 1 value
Type: string or number
root fcb_settings field0DA oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0DA oneOf item 2 bitfields
Type: object

root fcb_settings field0DA oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0DA oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0DA oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0DA oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0DA oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0DA oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0DA oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr6

lookupTable_seq5_instr6


Offset: 0x000000DC, Width: 16b; Lookup table holds Flash command sequences 5, instruction 6

root fcb_settings lookupTable_seq5_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0DC

lookupTable_seq5_instr6


Offset: 0x000000DC, Width: 16b; Lookup table holds Flash command sequences 5, instruction 6

root fcb_settings field0DC oneOf item 0
Type: string or number
root fcb_settings field0DC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0DC oneOf item 1 value
Type: string or number
root fcb_settings field0DC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0DC oneOf item 2 bitfields
Type: object

root fcb_settings field0DC oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0DC oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0DC oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0DC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0DC oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0DC oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0DC oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr7

lookupTable_seq5_instr7


Offset: 0x000000DE, Width: 16b; Lookup table holds Flash command sequences 5, instruction 7

root fcb_settings lookupTable_seq5_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq5_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq5_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq5_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq5_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq5_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq5_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0DE

lookupTable_seq5_instr7


Offset: 0x000000DE, Width: 16b; Lookup table holds Flash command sequences 5, instruction 7

root fcb_settings field0DE oneOf item 0
Type: string or number
root fcb_settings field0DE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0DE oneOf item 1 value
Type: string or number
root fcb_settings field0DE oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0DE oneOf item 2 bitfields
Type: object

root fcb_settings field0DE oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0DE oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0DE oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0DE oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0DE oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0DE oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0DE oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr0

lookupTable_seq6_instr0


Offset: 0x000000E0, Width: 16b; Lookup table holds Flash command sequences 6, instruction 0

root fcb_settings lookupTable_seq6_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E0

lookupTable_seq6_instr0


Offset: 0x000000E0, Width: 16b; Lookup table holds Flash command sequences 6, instruction 0

root fcb_settings field0E0 oneOf item 0
Type: string or number
root fcb_settings field0E0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0E0 oneOf item 1 value
Type: string or number
root fcb_settings field0E0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0E0 oneOf item 2 bitfields
Type: object

root fcb_settings field0E0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0E0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr1

lookupTable_seq6_instr1


Offset: 0x000000E2, Width: 16b; Lookup table holds Flash command sequences 6, instruction 1

root fcb_settings lookupTable_seq6_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E2

lookupTable_seq6_instr1


Offset: 0x000000E2, Width: 16b; Lookup table holds Flash command sequences 6, instruction 1

root fcb_settings field0E2 oneOf item 0
Type: string or number
root fcb_settings field0E2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0E2 oneOf item 1 value
Type: string or number
root fcb_settings field0E2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0E2 oneOf item 2 bitfields
Type: object

root fcb_settings field0E2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0E2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr2

lookupTable_seq6_instr2


Offset: 0x000000E4, Width: 16b; Lookup table holds Flash command sequences 6, instruction 2

root fcb_settings lookupTable_seq6_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E4

lookupTable_seq6_instr2


Offset: 0x000000E4, Width: 16b; Lookup table holds Flash command sequences 6, instruction 2

root fcb_settings field0E4 oneOf item 0
Type: string or number
root fcb_settings field0E4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0E4 oneOf item 1 value
Type: string or number
root fcb_settings field0E4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0E4 oneOf item 2 bitfields
Type: object

root fcb_settings field0E4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0E4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr3

lookupTable_seq6_instr3


Offset: 0x000000E6, Width: 16b; Lookup table holds Flash command sequences 6, instruction 3

root fcb_settings lookupTable_seq6_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E6

lookupTable_seq6_instr3


Offset: 0x000000E6, Width: 16b; Lookup table holds Flash command sequences 6, instruction 3

root fcb_settings field0E6 oneOf item 0
Type: string or number
root fcb_settings field0E6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0E6 oneOf item 1 value
Type: string or number
root fcb_settings field0E6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0E6 oneOf item 2 bitfields
Type: object

root fcb_settings field0E6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0E6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr4

lookupTable_seq6_instr4


Offset: 0x000000E8, Width: 16b; Lookup table holds Flash command sequences 6, instruction 4

root fcb_settings lookupTable_seq6_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E8

lookupTable_seq6_instr4


Offset: 0x000000E8, Width: 16b; Lookup table holds Flash command sequences 6, instruction 4

root fcb_settings field0E8 oneOf item 0
Type: string or number
root fcb_settings field0E8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0E8 oneOf item 1 value
Type: string or number
root fcb_settings field0E8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0E8 oneOf item 2 bitfields
Type: object

root fcb_settings field0E8 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E8 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E8 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0E8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0E8 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0E8 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0E8 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr5

lookupTable_seq6_instr5


Offset: 0x000000EA, Width: 16b; Lookup table holds Flash command sequences 6, instruction 5

root fcb_settings lookupTable_seq6_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0EA

lookupTable_seq6_instr5


Offset: 0x000000EA, Width: 16b; Lookup table holds Flash command sequences 6, instruction 5

root fcb_settings field0EA oneOf item 0
Type: string or number
root fcb_settings field0EA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0EA oneOf item 1 value
Type: string or number
root fcb_settings field0EA oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0EA oneOf item 2 bitfields
Type: object

root fcb_settings field0EA oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0EA oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0EA oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0EA oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0EA oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0EA oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0EA oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr6

lookupTable_seq6_instr6


Offset: 0x000000EC, Width: 16b; Lookup table holds Flash command sequences 6, instruction 6

root fcb_settings lookupTable_seq6_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0EC

lookupTable_seq6_instr6


Offset: 0x000000EC, Width: 16b; Lookup table holds Flash command sequences 6, instruction 6

root fcb_settings field0EC oneOf item 0
Type: string or number
root fcb_settings field0EC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0EC oneOf item 1 value
Type: string or number
root fcb_settings field0EC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0EC oneOf item 2 bitfields
Type: object

root fcb_settings field0EC oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0EC oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0EC oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0EC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0EC oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0EC oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0EC oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr7

lookupTable_seq6_instr7


Offset: 0x000000EE, Width: 16b; Lookup table holds Flash command sequences 6, instruction 7

root fcb_settings lookupTable_seq6_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq6_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq6_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq6_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq6_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq6_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq6_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0EE

lookupTable_seq6_instr7


Offset: 0x000000EE, Width: 16b; Lookup table holds Flash command sequences 6, instruction 7

root fcb_settings field0EE oneOf item 0
Type: string or number
root fcb_settings field0EE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0EE oneOf item 1 value
Type: string or number
root fcb_settings field0EE oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0EE oneOf item 2 bitfields
Type: object

root fcb_settings field0EE oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0EE oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0EE oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0EE oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0EE oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0EE oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0EE oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr0

lookupTable_seq7_instr0


Offset: 0x000000F0, Width: 16b; Lookup table holds Flash command sequences 7, instruction 0

root fcb_settings lookupTable_seq7_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F0

lookupTable_seq7_instr0


Offset: 0x000000F0, Width: 16b; Lookup table holds Flash command sequences 7, instruction 0

root fcb_settings field0F0 oneOf item 0
Type: string or number
root fcb_settings field0F0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0F0 oneOf item 1 value
Type: string or number
root fcb_settings field0F0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0F0 oneOf item 2 bitfields
Type: object

root fcb_settings field0F0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0F0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr1

lookupTable_seq7_instr1


Offset: 0x000000F2, Width: 16b; Lookup table holds Flash command sequences 7, instruction 1

root fcb_settings lookupTable_seq7_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F2

lookupTable_seq7_instr1


Offset: 0x000000F2, Width: 16b; Lookup table holds Flash command sequences 7, instruction 1

root fcb_settings field0F2 oneOf item 0
Type: string or number
root fcb_settings field0F2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0F2 oneOf item 1 value
Type: string or number
root fcb_settings field0F2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0F2 oneOf item 2 bitfields
Type: object

root fcb_settings field0F2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0F2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr2

lookupTable_seq7_instr2


Offset: 0x000000F4, Width: 16b; Lookup table holds Flash command sequences 7, instruction 2

root fcb_settings lookupTable_seq7_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F4

lookupTable_seq7_instr2


Offset: 0x000000F4, Width: 16b; Lookup table holds Flash command sequences 7, instruction 2

root fcb_settings field0F4 oneOf item 0
Type: string or number
root fcb_settings field0F4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0F4 oneOf item 1 value
Type: string or number
root fcb_settings field0F4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0F4 oneOf item 2 bitfields
Type: object

root fcb_settings field0F4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0F4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr3

lookupTable_seq7_instr3


Offset: 0x000000F6, Width: 16b; Lookup table holds Flash command sequences 7, instruction 3

root fcb_settings lookupTable_seq7_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F6

lookupTable_seq7_instr3


Offset: 0x000000F6, Width: 16b; Lookup table holds Flash command sequences 7, instruction 3

root fcb_settings field0F6 oneOf item 0
Type: string or number
root fcb_settings field0F6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0F6 oneOf item 1 value
Type: string or number
root fcb_settings field0F6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0F6 oneOf item 2 bitfields
Type: object

root fcb_settings field0F6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0F6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr4

lookupTable_seq7_instr4


Offset: 0x000000F8, Width: 16b; Lookup table holds Flash command sequences 7, instruction 4

root fcb_settings lookupTable_seq7_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F8

lookupTable_seq7_instr4


Offset: 0x000000F8, Width: 16b; Lookup table holds Flash command sequences 7, instruction 4

root fcb_settings field0F8 oneOf item 0
Type: string or number
root fcb_settings field0F8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0F8 oneOf item 1 value
Type: string or number
root fcb_settings field0F8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0F8 oneOf item 2 bitfields
Type: object

root fcb_settings field0F8 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F8 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F8 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0F8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0F8 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0F8 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0F8 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr5

lookupTable_seq7_instr5


Offset: 0x000000FA, Width: 16b; Lookup table holds Flash command sequences 7, instruction 5

root fcb_settings lookupTable_seq7_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0FA

lookupTable_seq7_instr5


Offset: 0x000000FA, Width: 16b; Lookup table holds Flash command sequences 7, instruction 5

root fcb_settings field0FA oneOf item 0
Type: string or number
root fcb_settings field0FA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0FA oneOf item 1 value
Type: string or number
root fcb_settings field0FA oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0FA oneOf item 2 bitfields
Type: object

root fcb_settings field0FA oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0FA oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0FA oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0FA oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0FA oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0FA oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0FA oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr6

lookupTable_seq7_instr6


Offset: 0x000000FC, Width: 16b; Lookup table holds Flash command sequences 7, instruction 6

root fcb_settings lookupTable_seq7_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0FC

lookupTable_seq7_instr6


Offset: 0x000000FC, Width: 16b; Lookup table holds Flash command sequences 7, instruction 6

root fcb_settings field0FC oneOf item 0
Type: string or number
root fcb_settings field0FC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0FC oneOf item 1 value
Type: string or number
root fcb_settings field0FC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0FC oneOf item 2 bitfields
Type: object

root fcb_settings field0FC oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0FC oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0FC oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0FC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0FC oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0FC oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0FC oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr7

lookupTable_seq7_instr7


Offset: 0x000000FE, Width: 16b; Lookup table holds Flash command sequences 7, instruction 7

root fcb_settings lookupTable_seq7_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq7_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq7_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq7_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq7_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq7_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq7_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0FE

lookupTable_seq7_instr7


Offset: 0x000000FE, Width: 16b; Lookup table holds Flash command sequences 7, instruction 7

root fcb_settings field0FE oneOf item 0
Type: string or number
root fcb_settings field0FE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field0FE oneOf item 1 value
Type: string or number
root fcb_settings field0FE oneOf item 2
Type: object
No Additional Properties

root fcb_settings field0FE oneOf item 2 bitfields
Type: object

root fcb_settings field0FE oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0FE oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0FE oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field0FE oneOf item 3
Type: object
No Additional Properties

root fcb_settings field0FE oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field0FE oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field0FE oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr0

lookupTable_seq8_instr0


Offset: 0x00000100, Width: 16b; Lookup table holds Flash command sequences 8, instruction 0

root fcb_settings lookupTable_seq8_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field100

lookupTable_seq8_instr0


Offset: 0x00000100, Width: 16b; Lookup table holds Flash command sequences 8, instruction 0

root fcb_settings field100 oneOf item 0
Type: string or number
root fcb_settings field100 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field100 oneOf item 1 value
Type: string or number
root fcb_settings field100 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field100 oneOf item 2 bitfields
Type: object

root fcb_settings field100 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field100 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field100 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field100 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field100 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field100 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field100 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr1

lookupTable_seq8_instr1


Offset: 0x00000102, Width: 16b; Lookup table holds Flash command sequences 8, instruction 1

root fcb_settings lookupTable_seq8_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field102

lookupTable_seq8_instr1


Offset: 0x00000102, Width: 16b; Lookup table holds Flash command sequences 8, instruction 1

root fcb_settings field102 oneOf item 0
Type: string or number
root fcb_settings field102 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field102 oneOf item 1 value
Type: string or number
root fcb_settings field102 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field102 oneOf item 2 bitfields
Type: object

root fcb_settings field102 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field102 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field102 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field102 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field102 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field102 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field102 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr2

lookupTable_seq8_instr2


Offset: 0x00000104, Width: 16b; Lookup table holds Flash command sequences 8, instruction 2

root fcb_settings lookupTable_seq8_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field104

lookupTable_seq8_instr2


Offset: 0x00000104, Width: 16b; Lookup table holds Flash command sequences 8, instruction 2

root fcb_settings field104 oneOf item 0
Type: string or number
root fcb_settings field104 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field104 oneOf item 1 value
Type: string or number
root fcb_settings field104 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field104 oneOf item 2 bitfields
Type: object

root fcb_settings field104 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field104 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field104 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field104 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field104 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field104 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field104 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr3

lookupTable_seq8_instr3


Offset: 0x00000106, Width: 16b; Lookup table holds Flash command sequences 8, instruction 3

root fcb_settings lookupTable_seq8_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field106

lookupTable_seq8_instr3


Offset: 0x00000106, Width: 16b; Lookup table holds Flash command sequences 8, instruction 3

root fcb_settings field106 oneOf item 0
Type: string or number
root fcb_settings field106 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field106 oneOf item 1 value
Type: string or number
root fcb_settings field106 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field106 oneOf item 2 bitfields
Type: object

root fcb_settings field106 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field106 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field106 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field106 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field106 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field106 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field106 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr4

lookupTable_seq8_instr4


Offset: 0x00000108, Width: 16b; Lookup table holds Flash command sequences 8, instruction 4

root fcb_settings lookupTable_seq8_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field108

lookupTable_seq8_instr4


Offset: 0x00000108, Width: 16b; Lookup table holds Flash command sequences 8, instruction 4

root fcb_settings field108 oneOf item 0
Type: string or number
root fcb_settings field108 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field108 oneOf item 1 value
Type: string or number
root fcb_settings field108 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field108 oneOf item 2 bitfields
Type: object

root fcb_settings field108 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field108 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field108 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field108 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field108 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field108 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field108 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr5

lookupTable_seq8_instr5


Offset: 0x0000010A, Width: 16b; Lookup table holds Flash command sequences 8, instruction 5

root fcb_settings lookupTable_seq8_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field10A

lookupTable_seq8_instr5


Offset: 0x0000010A, Width: 16b; Lookup table holds Flash command sequences 8, instruction 5

root fcb_settings field10A oneOf item 0
Type: string or number
root fcb_settings field10A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field10A oneOf item 1 value
Type: string or number
root fcb_settings field10A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field10A oneOf item 2 bitfields
Type: object

root fcb_settings field10A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field10A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field10A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field10A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field10A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field10A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field10A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr6

lookupTable_seq8_instr6


Offset: 0x0000010C, Width: 16b; Lookup table holds Flash command sequences 8, instruction 6

root fcb_settings lookupTable_seq8_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field10C

lookupTable_seq8_instr6


Offset: 0x0000010C, Width: 16b; Lookup table holds Flash command sequences 8, instruction 6

root fcb_settings field10C oneOf item 0
Type: string or number
root fcb_settings field10C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field10C oneOf item 1 value
Type: string or number
root fcb_settings field10C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field10C oneOf item 2 bitfields
Type: object

root fcb_settings field10C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field10C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field10C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field10C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field10C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field10C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field10C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr7

lookupTable_seq8_instr7


Offset: 0x0000010E, Width: 16b; Lookup table holds Flash command sequences 8, instruction 7

root fcb_settings lookupTable_seq8_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq8_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq8_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq8_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq8_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq8_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq8_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field10E

lookupTable_seq8_instr7


Offset: 0x0000010E, Width: 16b; Lookup table holds Flash command sequences 8, instruction 7

root fcb_settings field10E oneOf item 0
Type: string or number
root fcb_settings field10E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field10E oneOf item 1 value
Type: string or number
root fcb_settings field10E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field10E oneOf item 2 bitfields
Type: object

root fcb_settings field10E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field10E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field10E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field10E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field10E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field10E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field10E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr0

lookupTable_seq9_instr0


Offset: 0x00000110, Width: 16b; Lookup table holds Flash command sequences 9, instruction 0

root fcb_settings lookupTable_seq9_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field110

lookupTable_seq9_instr0


Offset: 0x00000110, Width: 16b; Lookup table holds Flash command sequences 9, instruction 0

root fcb_settings field110 oneOf item 0
Type: string or number
root fcb_settings field110 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field110 oneOf item 1 value
Type: string or number
root fcb_settings field110 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field110 oneOf item 2 bitfields
Type: object

root fcb_settings field110 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field110 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field110 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field110 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field110 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field110 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field110 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr1

lookupTable_seq9_instr1


Offset: 0x00000112, Width: 16b; Lookup table holds Flash command sequences 9, instruction 1

root fcb_settings lookupTable_seq9_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field112

lookupTable_seq9_instr1


Offset: 0x00000112, Width: 16b; Lookup table holds Flash command sequences 9, instruction 1

root fcb_settings field112 oneOf item 0
Type: string or number
root fcb_settings field112 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field112 oneOf item 1 value
Type: string or number
root fcb_settings field112 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field112 oneOf item 2 bitfields
Type: object

root fcb_settings field112 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field112 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field112 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field112 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field112 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field112 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field112 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr2

lookupTable_seq9_instr2


Offset: 0x00000114, Width: 16b; Lookup table holds Flash command sequences 9, instruction 2

root fcb_settings lookupTable_seq9_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field114

lookupTable_seq9_instr2


Offset: 0x00000114, Width: 16b; Lookup table holds Flash command sequences 9, instruction 2

root fcb_settings field114 oneOf item 0
Type: string or number
root fcb_settings field114 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field114 oneOf item 1 value
Type: string or number
root fcb_settings field114 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field114 oneOf item 2 bitfields
Type: object

root fcb_settings field114 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field114 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field114 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field114 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field114 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field114 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field114 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr3

lookupTable_seq9_instr3


Offset: 0x00000116, Width: 16b; Lookup table holds Flash command sequences 9, instruction 3

root fcb_settings lookupTable_seq9_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field116

lookupTable_seq9_instr3


Offset: 0x00000116, Width: 16b; Lookup table holds Flash command sequences 9, instruction 3

root fcb_settings field116 oneOf item 0
Type: string or number
root fcb_settings field116 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field116 oneOf item 1 value
Type: string or number
root fcb_settings field116 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field116 oneOf item 2 bitfields
Type: object

root fcb_settings field116 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field116 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field116 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field116 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field116 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field116 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field116 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr4

lookupTable_seq9_instr4


Offset: 0x00000118, Width: 16b; Lookup table holds Flash command sequences 9, instruction 4

root fcb_settings lookupTable_seq9_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field118

lookupTable_seq9_instr4


Offset: 0x00000118, Width: 16b; Lookup table holds Flash command sequences 9, instruction 4

root fcb_settings field118 oneOf item 0
Type: string or number
root fcb_settings field118 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field118 oneOf item 1 value
Type: string or number
root fcb_settings field118 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field118 oneOf item 2 bitfields
Type: object

root fcb_settings field118 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field118 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field118 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field118 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field118 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field118 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field118 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr5

lookupTable_seq9_instr5


Offset: 0x0000011A, Width: 16b; Lookup table holds Flash command sequences 9, instruction 5

root fcb_settings lookupTable_seq9_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field11A

lookupTable_seq9_instr5


Offset: 0x0000011A, Width: 16b; Lookup table holds Flash command sequences 9, instruction 5

root fcb_settings field11A oneOf item 0
Type: string or number
root fcb_settings field11A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field11A oneOf item 1 value
Type: string or number
root fcb_settings field11A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field11A oneOf item 2 bitfields
Type: object

root fcb_settings field11A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field11A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field11A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field11A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field11A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field11A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field11A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr6

lookupTable_seq9_instr6


Offset: 0x0000011C, Width: 16b; Lookup table holds Flash command sequences 9, instruction 6

root fcb_settings lookupTable_seq9_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field11C

lookupTable_seq9_instr6


Offset: 0x0000011C, Width: 16b; Lookup table holds Flash command sequences 9, instruction 6

root fcb_settings field11C oneOf item 0
Type: string or number
root fcb_settings field11C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field11C oneOf item 1 value
Type: string or number
root fcb_settings field11C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field11C oneOf item 2 bitfields
Type: object

root fcb_settings field11C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field11C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field11C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field11C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field11C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field11C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field11C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr7

lookupTable_seq9_instr7


Offset: 0x0000011E, Width: 16b; Lookup table holds Flash command sequences 9, instruction 7

root fcb_settings lookupTable_seq9_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq9_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq9_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq9_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq9_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq9_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq9_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field11E

lookupTable_seq9_instr7


Offset: 0x0000011E, Width: 16b; Lookup table holds Flash command sequences 9, instruction 7

root fcb_settings field11E oneOf item 0
Type: string or number
root fcb_settings field11E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field11E oneOf item 1 value
Type: string or number
root fcb_settings field11E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field11E oneOf item 2 bitfields
Type: object

root fcb_settings field11E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field11E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field11E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field11E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field11E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field11E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field11E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr0

lookupTable_seq10_instr0


Offset: 0x00000120, Width: 16b; Lookup table holds Flash command sequences 10, instruction 0

root fcb_settings lookupTable_seq10_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field120

lookupTable_seq10_instr0


Offset: 0x00000120, Width: 16b; Lookup table holds Flash command sequences 10, instruction 0

root fcb_settings field120 oneOf item 0
Type: string or number
root fcb_settings field120 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field120 oneOf item 1 value
Type: string or number
root fcb_settings field120 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field120 oneOf item 2 bitfields
Type: object

root fcb_settings field120 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field120 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field120 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field120 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field120 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field120 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field120 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr1

lookupTable_seq10_instr1


Offset: 0x00000122, Width: 16b; Lookup table holds Flash command sequences 10, instruction 1

root fcb_settings lookupTable_seq10_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field122

lookupTable_seq10_instr1


Offset: 0x00000122, Width: 16b; Lookup table holds Flash command sequences 10, instruction 1

root fcb_settings field122 oneOf item 0
Type: string or number
root fcb_settings field122 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field122 oneOf item 1 value
Type: string or number
root fcb_settings field122 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field122 oneOf item 2 bitfields
Type: object

root fcb_settings field122 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field122 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field122 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field122 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field122 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field122 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field122 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr2

lookupTable_seq10_instr2


Offset: 0x00000124, Width: 16b; Lookup table holds Flash command sequences 10, instruction 2

root fcb_settings lookupTable_seq10_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field124

lookupTable_seq10_instr2


Offset: 0x00000124, Width: 16b; Lookup table holds Flash command sequences 10, instruction 2

root fcb_settings field124 oneOf item 0
Type: string or number
root fcb_settings field124 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field124 oneOf item 1 value
Type: string or number
root fcb_settings field124 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field124 oneOf item 2 bitfields
Type: object

root fcb_settings field124 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field124 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field124 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field124 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field124 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field124 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field124 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr3

lookupTable_seq10_instr3


Offset: 0x00000126, Width: 16b; Lookup table holds Flash command sequences 10, instruction 3

root fcb_settings lookupTable_seq10_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field126

lookupTable_seq10_instr3


Offset: 0x00000126, Width: 16b; Lookup table holds Flash command sequences 10, instruction 3

root fcb_settings field126 oneOf item 0
Type: string or number
root fcb_settings field126 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field126 oneOf item 1 value
Type: string or number
root fcb_settings field126 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field126 oneOf item 2 bitfields
Type: object

root fcb_settings field126 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field126 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field126 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field126 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field126 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field126 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field126 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr4

lookupTable_seq10_instr4


Offset: 0x00000128, Width: 16b; Lookup table holds Flash command sequences 10, instruction 4

root fcb_settings lookupTable_seq10_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field128

lookupTable_seq10_instr4


Offset: 0x00000128, Width: 16b; Lookup table holds Flash command sequences 10, instruction 4

root fcb_settings field128 oneOf item 0
Type: string or number
root fcb_settings field128 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field128 oneOf item 1 value
Type: string or number
root fcb_settings field128 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field128 oneOf item 2 bitfields
Type: object

root fcb_settings field128 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field128 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field128 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field128 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field128 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field128 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field128 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr5

lookupTable_seq10_instr5


Offset: 0x0000012A, Width: 16b; Lookup table holds Flash command sequences 10, instruction 5

root fcb_settings lookupTable_seq10_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field12A

lookupTable_seq10_instr5


Offset: 0x0000012A, Width: 16b; Lookup table holds Flash command sequences 10, instruction 5

root fcb_settings field12A oneOf item 0
Type: string or number
root fcb_settings field12A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field12A oneOf item 1 value
Type: string or number
root fcb_settings field12A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field12A oneOf item 2 bitfields
Type: object

root fcb_settings field12A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field12A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field12A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field12A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field12A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field12A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field12A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr6

lookupTable_seq10_instr6


Offset: 0x0000012C, Width: 16b; Lookup table holds Flash command sequences 10, instruction 6

root fcb_settings lookupTable_seq10_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field12C

lookupTable_seq10_instr6


Offset: 0x0000012C, Width: 16b; Lookup table holds Flash command sequences 10, instruction 6

root fcb_settings field12C oneOf item 0
Type: string or number
root fcb_settings field12C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field12C oneOf item 1 value
Type: string or number
root fcb_settings field12C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field12C oneOf item 2 bitfields
Type: object

root fcb_settings field12C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field12C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field12C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field12C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field12C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field12C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field12C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr7

lookupTable_seq10_instr7


Offset: 0x0000012E, Width: 16b; Lookup table holds Flash command sequences 10, instruction 7

root fcb_settings lookupTable_seq10_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq10_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq10_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq10_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq10_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq10_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq10_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field12E

lookupTable_seq10_instr7


Offset: 0x0000012E, Width: 16b; Lookup table holds Flash command sequences 10, instruction 7

root fcb_settings field12E oneOf item 0
Type: string or number
root fcb_settings field12E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field12E oneOf item 1 value
Type: string or number
root fcb_settings field12E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field12E oneOf item 2 bitfields
Type: object

root fcb_settings field12E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field12E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field12E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field12E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field12E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field12E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field12E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr0

lookupTable_seq11_instr0


Offset: 0x00000130, Width: 16b; Lookup table holds Flash command sequences 11, instruction 0

root fcb_settings lookupTable_seq11_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field130

lookupTable_seq11_instr0


Offset: 0x00000130, Width: 16b; Lookup table holds Flash command sequences 11, instruction 0

root fcb_settings field130 oneOf item 0
Type: string or number
root fcb_settings field130 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field130 oneOf item 1 value
Type: string or number
root fcb_settings field130 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field130 oneOf item 2 bitfields
Type: object

root fcb_settings field130 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field130 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field130 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field130 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field130 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field130 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field130 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr1

lookupTable_seq11_instr1


Offset: 0x00000132, Width: 16b; Lookup table holds Flash command sequences 11, instruction 1

root fcb_settings lookupTable_seq11_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field132

lookupTable_seq11_instr1


Offset: 0x00000132, Width: 16b; Lookup table holds Flash command sequences 11, instruction 1

root fcb_settings field132 oneOf item 0
Type: string or number
root fcb_settings field132 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field132 oneOf item 1 value
Type: string or number
root fcb_settings field132 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field132 oneOf item 2 bitfields
Type: object

root fcb_settings field132 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field132 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field132 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field132 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field132 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field132 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field132 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr2

lookupTable_seq11_instr2


Offset: 0x00000134, Width: 16b; Lookup table holds Flash command sequences 11, instruction 2

root fcb_settings lookupTable_seq11_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field134

lookupTable_seq11_instr2


Offset: 0x00000134, Width: 16b; Lookup table holds Flash command sequences 11, instruction 2

root fcb_settings field134 oneOf item 0
Type: string or number
root fcb_settings field134 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field134 oneOf item 1 value
Type: string or number
root fcb_settings field134 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field134 oneOf item 2 bitfields
Type: object

root fcb_settings field134 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field134 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field134 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field134 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field134 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field134 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field134 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr3

lookupTable_seq11_instr3


Offset: 0x00000136, Width: 16b; Lookup table holds Flash command sequences 11, instruction 3

root fcb_settings lookupTable_seq11_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field136

lookupTable_seq11_instr3


Offset: 0x00000136, Width: 16b; Lookup table holds Flash command sequences 11, instruction 3

root fcb_settings field136 oneOf item 0
Type: string or number
root fcb_settings field136 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field136 oneOf item 1 value
Type: string or number
root fcb_settings field136 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field136 oneOf item 2 bitfields
Type: object

root fcb_settings field136 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field136 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field136 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field136 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field136 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field136 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field136 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr4

lookupTable_seq11_instr4


Offset: 0x00000138, Width: 16b; Lookup table holds Flash command sequences 11, instruction 4

root fcb_settings lookupTable_seq11_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field138

lookupTable_seq11_instr4


Offset: 0x00000138, Width: 16b; Lookup table holds Flash command sequences 11, instruction 4

root fcb_settings field138 oneOf item 0
Type: string or number
root fcb_settings field138 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field138 oneOf item 1 value
Type: string or number
root fcb_settings field138 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field138 oneOf item 2 bitfields
Type: object

root fcb_settings field138 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field138 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field138 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field138 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field138 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field138 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field138 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr5

lookupTable_seq11_instr5


Offset: 0x0000013A, Width: 16b; Lookup table holds Flash command sequences 11, instruction 5

root fcb_settings lookupTable_seq11_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field13A

lookupTable_seq11_instr5


Offset: 0x0000013A, Width: 16b; Lookup table holds Flash command sequences 11, instruction 5

root fcb_settings field13A oneOf item 0
Type: string or number
root fcb_settings field13A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field13A oneOf item 1 value
Type: string or number
root fcb_settings field13A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field13A oneOf item 2 bitfields
Type: object

root fcb_settings field13A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field13A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field13A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field13A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field13A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field13A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field13A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr6

lookupTable_seq11_instr6


Offset: 0x0000013C, Width: 16b; Lookup table holds Flash command sequences 11, instruction 6

root fcb_settings lookupTable_seq11_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field13C

lookupTable_seq11_instr6


Offset: 0x0000013C, Width: 16b; Lookup table holds Flash command sequences 11, instruction 6

root fcb_settings field13C oneOf item 0
Type: string or number
root fcb_settings field13C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field13C oneOf item 1 value
Type: string or number
root fcb_settings field13C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field13C oneOf item 2 bitfields
Type: object

root fcb_settings field13C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field13C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field13C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field13C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field13C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field13C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field13C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr7

lookupTable_seq11_instr7


Offset: 0x0000013E, Width: 16b; Lookup table holds Flash command sequences 11, instruction 7

root fcb_settings lookupTable_seq11_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq11_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq11_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq11_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq11_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq11_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq11_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field13E

lookupTable_seq11_instr7


Offset: 0x0000013E, Width: 16b; Lookup table holds Flash command sequences 11, instruction 7

root fcb_settings field13E oneOf item 0
Type: string or number
root fcb_settings field13E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field13E oneOf item 1 value
Type: string or number
root fcb_settings field13E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field13E oneOf item 2 bitfields
Type: object

root fcb_settings field13E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field13E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field13E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field13E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field13E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field13E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field13E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr0

lookupTable_seq12_instr0


Offset: 0x00000140, Width: 16b; Lookup table holds Flash command sequences 12, instruction 0

root fcb_settings lookupTable_seq12_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field140

lookupTable_seq12_instr0


Offset: 0x00000140, Width: 16b; Lookup table holds Flash command sequences 12, instruction 0

root fcb_settings field140 oneOf item 0
Type: string or number
root fcb_settings field140 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field140 oneOf item 1 value
Type: string or number
root fcb_settings field140 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field140 oneOf item 2 bitfields
Type: object

root fcb_settings field140 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field140 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field140 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field140 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field140 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field140 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field140 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr1

lookupTable_seq12_instr1


Offset: 0x00000142, Width: 16b; Lookup table holds Flash command sequences 12, instruction 1

root fcb_settings lookupTable_seq12_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field142

lookupTable_seq12_instr1


Offset: 0x00000142, Width: 16b; Lookup table holds Flash command sequences 12, instruction 1

root fcb_settings field142 oneOf item 0
Type: string or number
root fcb_settings field142 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field142 oneOf item 1 value
Type: string or number
root fcb_settings field142 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field142 oneOf item 2 bitfields
Type: object

root fcb_settings field142 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field142 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field142 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field142 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field142 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field142 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field142 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr2

lookupTable_seq12_instr2


Offset: 0x00000144, Width: 16b; Lookup table holds Flash command sequences 12, instruction 2

root fcb_settings lookupTable_seq12_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field144

lookupTable_seq12_instr2


Offset: 0x00000144, Width: 16b; Lookup table holds Flash command sequences 12, instruction 2

root fcb_settings field144 oneOf item 0
Type: string or number
root fcb_settings field144 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field144 oneOf item 1 value
Type: string or number
root fcb_settings field144 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field144 oneOf item 2 bitfields
Type: object

root fcb_settings field144 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field144 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field144 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field144 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field144 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field144 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field144 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr3

lookupTable_seq12_instr3


Offset: 0x00000146, Width: 16b; Lookup table holds Flash command sequences 12, instruction 3

root fcb_settings lookupTable_seq12_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field146

lookupTable_seq12_instr3


Offset: 0x00000146, Width: 16b; Lookup table holds Flash command sequences 12, instruction 3

root fcb_settings field146 oneOf item 0
Type: string or number
root fcb_settings field146 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field146 oneOf item 1 value
Type: string or number
root fcb_settings field146 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field146 oneOf item 2 bitfields
Type: object

root fcb_settings field146 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field146 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field146 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field146 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field146 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field146 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field146 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr4

lookupTable_seq12_instr4


Offset: 0x00000148, Width: 16b; Lookup table holds Flash command sequences 12, instruction 4

root fcb_settings lookupTable_seq12_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field148

lookupTable_seq12_instr4


Offset: 0x00000148, Width: 16b; Lookup table holds Flash command sequences 12, instruction 4

root fcb_settings field148 oneOf item 0
Type: string or number
root fcb_settings field148 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field148 oneOf item 1 value
Type: string or number
root fcb_settings field148 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field148 oneOf item 2 bitfields
Type: object

root fcb_settings field148 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field148 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field148 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field148 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field148 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field148 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field148 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr5

lookupTable_seq12_instr5


Offset: 0x0000014A, Width: 16b; Lookup table holds Flash command sequences 12, instruction 5

root fcb_settings lookupTable_seq12_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field14A

lookupTable_seq12_instr5


Offset: 0x0000014A, Width: 16b; Lookup table holds Flash command sequences 12, instruction 5

root fcb_settings field14A oneOf item 0
Type: string or number
root fcb_settings field14A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field14A oneOf item 1 value
Type: string or number
root fcb_settings field14A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field14A oneOf item 2 bitfields
Type: object

root fcb_settings field14A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field14A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field14A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field14A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field14A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field14A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field14A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr6

lookupTable_seq12_instr6


Offset: 0x0000014C, Width: 16b; Lookup table holds Flash command sequences 12, instruction 6

root fcb_settings lookupTable_seq12_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field14C

lookupTable_seq12_instr6


Offset: 0x0000014C, Width: 16b; Lookup table holds Flash command sequences 12, instruction 6

root fcb_settings field14C oneOf item 0
Type: string or number
root fcb_settings field14C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field14C oneOf item 1 value
Type: string or number
root fcb_settings field14C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field14C oneOf item 2 bitfields
Type: object

root fcb_settings field14C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field14C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field14C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field14C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field14C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field14C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field14C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr7

lookupTable_seq12_instr7


Offset: 0x0000014E, Width: 16b; Lookup table holds Flash command sequences 12, instruction 7

root fcb_settings lookupTable_seq12_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq12_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq12_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq12_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq12_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq12_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq12_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field14E

lookupTable_seq12_instr7


Offset: 0x0000014E, Width: 16b; Lookup table holds Flash command sequences 12, instruction 7

root fcb_settings field14E oneOf item 0
Type: string or number
root fcb_settings field14E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field14E oneOf item 1 value
Type: string or number
root fcb_settings field14E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field14E oneOf item 2 bitfields
Type: object

root fcb_settings field14E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field14E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field14E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field14E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field14E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field14E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field14E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr0

lookupTable_seq13_instr0


Offset: 0x00000150, Width: 16b; Lookup table holds Flash command sequences 13, instruction 0

root fcb_settings lookupTable_seq13_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field150

lookupTable_seq13_instr0


Offset: 0x00000150, Width: 16b; Lookup table holds Flash command sequences 13, instruction 0

root fcb_settings field150 oneOf item 0
Type: string or number
root fcb_settings field150 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field150 oneOf item 1 value
Type: string or number
root fcb_settings field150 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field150 oneOf item 2 bitfields
Type: object

root fcb_settings field150 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field150 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field150 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field150 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field150 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field150 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field150 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr1

lookupTable_seq13_instr1


Offset: 0x00000152, Width: 16b; Lookup table holds Flash command sequences 13, instruction 1

root fcb_settings lookupTable_seq13_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field152

lookupTable_seq13_instr1


Offset: 0x00000152, Width: 16b; Lookup table holds Flash command sequences 13, instruction 1

root fcb_settings field152 oneOf item 0
Type: string or number
root fcb_settings field152 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field152 oneOf item 1 value
Type: string or number
root fcb_settings field152 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field152 oneOf item 2 bitfields
Type: object

root fcb_settings field152 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field152 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field152 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field152 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field152 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field152 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field152 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr2

lookupTable_seq13_instr2


Offset: 0x00000154, Width: 16b; Lookup table holds Flash command sequences 13, instruction 2

root fcb_settings lookupTable_seq13_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field154

lookupTable_seq13_instr2


Offset: 0x00000154, Width: 16b; Lookup table holds Flash command sequences 13, instruction 2

root fcb_settings field154 oneOf item 0
Type: string or number
root fcb_settings field154 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field154 oneOf item 1 value
Type: string or number
root fcb_settings field154 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field154 oneOf item 2 bitfields
Type: object

root fcb_settings field154 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field154 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field154 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field154 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field154 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field154 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field154 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr3

lookupTable_seq13_instr3


Offset: 0x00000156, Width: 16b; Lookup table holds Flash command sequences 13, instruction 3

root fcb_settings lookupTable_seq13_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field156

lookupTable_seq13_instr3


Offset: 0x00000156, Width: 16b; Lookup table holds Flash command sequences 13, instruction 3

root fcb_settings field156 oneOf item 0
Type: string or number
root fcb_settings field156 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field156 oneOf item 1 value
Type: string or number
root fcb_settings field156 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field156 oneOf item 2 bitfields
Type: object

root fcb_settings field156 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field156 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field156 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field156 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field156 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field156 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field156 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr4

lookupTable_seq13_instr4


Offset: 0x00000158, Width: 16b; Lookup table holds Flash command sequences 13, instruction 4

root fcb_settings lookupTable_seq13_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field158

lookupTable_seq13_instr4


Offset: 0x00000158, Width: 16b; Lookup table holds Flash command sequences 13, instruction 4

root fcb_settings field158 oneOf item 0
Type: string or number
root fcb_settings field158 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field158 oneOf item 1 value
Type: string or number
root fcb_settings field158 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field158 oneOf item 2 bitfields
Type: object

root fcb_settings field158 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field158 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field158 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field158 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field158 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field158 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field158 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr5

lookupTable_seq13_instr5


Offset: 0x0000015A, Width: 16b; Lookup table holds Flash command sequences 13, instruction 5

root fcb_settings lookupTable_seq13_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field15A

lookupTable_seq13_instr5


Offset: 0x0000015A, Width: 16b; Lookup table holds Flash command sequences 13, instruction 5

root fcb_settings field15A oneOf item 0
Type: string or number
root fcb_settings field15A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field15A oneOf item 1 value
Type: string or number
root fcb_settings field15A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field15A oneOf item 2 bitfields
Type: object

root fcb_settings field15A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field15A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field15A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field15A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field15A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field15A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field15A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr6

lookupTable_seq13_instr6


Offset: 0x0000015C, Width: 16b; Lookup table holds Flash command sequences 13, instruction 6

root fcb_settings lookupTable_seq13_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field15C

lookupTable_seq13_instr6


Offset: 0x0000015C, Width: 16b; Lookup table holds Flash command sequences 13, instruction 6

root fcb_settings field15C oneOf item 0
Type: string or number
root fcb_settings field15C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field15C oneOf item 1 value
Type: string or number
root fcb_settings field15C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field15C oneOf item 2 bitfields
Type: object

root fcb_settings field15C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field15C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field15C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field15C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field15C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field15C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field15C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr7

lookupTable_seq13_instr7


Offset: 0x0000015E, Width: 16b; Lookup table holds Flash command sequences 13, instruction 7

root fcb_settings lookupTable_seq13_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq13_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq13_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq13_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq13_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq13_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq13_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field15E

lookupTable_seq13_instr7


Offset: 0x0000015E, Width: 16b; Lookup table holds Flash command sequences 13, instruction 7

root fcb_settings field15E oneOf item 0
Type: string or number
root fcb_settings field15E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field15E oneOf item 1 value
Type: string or number
root fcb_settings field15E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field15E oneOf item 2 bitfields
Type: object

root fcb_settings field15E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field15E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field15E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field15E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field15E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field15E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field15E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr0

lookupTable_seq14_instr0


Offset: 0x00000160, Width: 16b; Lookup table holds Flash command sequences 14, instruction 0

root fcb_settings lookupTable_seq14_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field160

lookupTable_seq14_instr0


Offset: 0x00000160, Width: 16b; Lookup table holds Flash command sequences 14, instruction 0

root fcb_settings field160 oneOf item 0
Type: string or number
root fcb_settings field160 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field160 oneOf item 1 value
Type: string or number
root fcb_settings field160 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field160 oneOf item 2 bitfields
Type: object

root fcb_settings field160 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field160 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field160 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field160 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field160 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field160 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field160 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr1

lookupTable_seq14_instr1


Offset: 0x00000162, Width: 16b; Lookup table holds Flash command sequences 14, instruction 1

root fcb_settings lookupTable_seq14_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field162

lookupTable_seq14_instr1


Offset: 0x00000162, Width: 16b; Lookup table holds Flash command sequences 14, instruction 1

root fcb_settings field162 oneOf item 0
Type: string or number
root fcb_settings field162 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field162 oneOf item 1 value
Type: string or number
root fcb_settings field162 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field162 oneOf item 2 bitfields
Type: object

root fcb_settings field162 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field162 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field162 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field162 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field162 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field162 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field162 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr2

lookupTable_seq14_instr2


Offset: 0x00000164, Width: 16b; Lookup table holds Flash command sequences 14, instruction 2

root fcb_settings lookupTable_seq14_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field164

lookupTable_seq14_instr2


Offset: 0x00000164, Width: 16b; Lookup table holds Flash command sequences 14, instruction 2

root fcb_settings field164 oneOf item 0
Type: string or number
root fcb_settings field164 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field164 oneOf item 1 value
Type: string or number
root fcb_settings field164 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field164 oneOf item 2 bitfields
Type: object

root fcb_settings field164 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field164 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field164 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field164 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field164 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field164 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field164 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr3

lookupTable_seq14_instr3


Offset: 0x00000166, Width: 16b; Lookup table holds Flash command sequences 14, instruction 3

root fcb_settings lookupTable_seq14_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field166

lookupTable_seq14_instr3


Offset: 0x00000166, Width: 16b; Lookup table holds Flash command sequences 14, instruction 3

root fcb_settings field166 oneOf item 0
Type: string or number
root fcb_settings field166 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field166 oneOf item 1 value
Type: string or number
root fcb_settings field166 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field166 oneOf item 2 bitfields
Type: object

root fcb_settings field166 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field166 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field166 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field166 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field166 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field166 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field166 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr4

lookupTable_seq14_instr4


Offset: 0x00000168, Width: 16b; Lookup table holds Flash command sequences 14, instruction 4

root fcb_settings lookupTable_seq14_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field168

lookupTable_seq14_instr4


Offset: 0x00000168, Width: 16b; Lookup table holds Flash command sequences 14, instruction 4

root fcb_settings field168 oneOf item 0
Type: string or number
root fcb_settings field168 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field168 oneOf item 1 value
Type: string or number
root fcb_settings field168 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field168 oneOf item 2 bitfields
Type: object

root fcb_settings field168 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field168 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field168 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field168 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field168 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field168 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field168 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr5

lookupTable_seq14_instr5


Offset: 0x0000016A, Width: 16b; Lookup table holds Flash command sequences 14, instruction 5

root fcb_settings lookupTable_seq14_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field16A

lookupTable_seq14_instr5


Offset: 0x0000016A, Width: 16b; Lookup table holds Flash command sequences 14, instruction 5

root fcb_settings field16A oneOf item 0
Type: string or number
root fcb_settings field16A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field16A oneOf item 1 value
Type: string or number
root fcb_settings field16A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field16A oneOf item 2 bitfields
Type: object

root fcb_settings field16A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field16A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field16A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field16A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field16A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field16A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field16A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr6

lookupTable_seq14_instr6


Offset: 0x0000016C, Width: 16b; Lookup table holds Flash command sequences 14, instruction 6

root fcb_settings lookupTable_seq14_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field16C

lookupTable_seq14_instr6


Offset: 0x0000016C, Width: 16b; Lookup table holds Flash command sequences 14, instruction 6

root fcb_settings field16C oneOf item 0
Type: string or number
root fcb_settings field16C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field16C oneOf item 1 value
Type: string or number
root fcb_settings field16C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field16C oneOf item 2 bitfields
Type: object

root fcb_settings field16C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field16C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field16C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field16C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field16C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field16C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field16C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr7

lookupTable_seq14_instr7


Offset: 0x0000016E, Width: 16b; Lookup table holds Flash command sequences 14, instruction 7

root fcb_settings lookupTable_seq14_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq14_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq14_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq14_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq14_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq14_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq14_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field16E

lookupTable_seq14_instr7


Offset: 0x0000016E, Width: 16b; Lookup table holds Flash command sequences 14, instruction 7

root fcb_settings field16E oneOf item 0
Type: string or number
root fcb_settings field16E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field16E oneOf item 1 value
Type: string or number
root fcb_settings field16E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field16E oneOf item 2 bitfields
Type: object

root fcb_settings field16E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field16E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field16E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field16E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field16E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field16E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field16E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr0

lookupTable_seq15_instr0


Offset: 0x00000170, Width: 16b; Lookup table holds Flash command sequences 15, instruction 0

root fcb_settings lookupTable_seq15_instr0 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr0 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr0 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr0 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr0 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr0 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr0 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr0 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field170

lookupTable_seq15_instr0


Offset: 0x00000170, Width: 16b; Lookup table holds Flash command sequences 15, instruction 0

root fcb_settings field170 oneOf item 0
Type: string or number
root fcb_settings field170 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field170 oneOf item 1 value
Type: string or number
root fcb_settings field170 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field170 oneOf item 2 bitfields
Type: object

root fcb_settings field170 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field170 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field170 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field170 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field170 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field170 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field170 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr1

lookupTable_seq15_instr1


Offset: 0x00000172, Width: 16b; Lookup table holds Flash command sequences 15, instruction 1

root fcb_settings lookupTable_seq15_instr1 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr1 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr1 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr1 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr1 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr1 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr1 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr1 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field172

lookupTable_seq15_instr1


Offset: 0x00000172, Width: 16b; Lookup table holds Flash command sequences 15, instruction 1

root fcb_settings field172 oneOf item 0
Type: string or number
root fcb_settings field172 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field172 oneOf item 1 value
Type: string or number
root fcb_settings field172 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field172 oneOf item 2 bitfields
Type: object

root fcb_settings field172 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field172 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field172 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field172 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field172 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field172 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field172 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr2

lookupTable_seq15_instr2


Offset: 0x00000174, Width: 16b; Lookup table holds Flash command sequences 15, instruction 2

root fcb_settings lookupTable_seq15_instr2 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr2 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr2 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr2 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr2 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr2 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr2 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr2 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field174

lookupTable_seq15_instr2


Offset: 0x00000174, Width: 16b; Lookup table holds Flash command sequences 15, instruction 2

root fcb_settings field174 oneOf item 0
Type: string or number
root fcb_settings field174 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field174 oneOf item 1 value
Type: string or number
root fcb_settings field174 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field174 oneOf item 2 bitfields
Type: object

root fcb_settings field174 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field174 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field174 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field174 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field174 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field174 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field174 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr3

lookupTable_seq15_instr3


Offset: 0x00000176, Width: 16b; Lookup table holds Flash command sequences 15, instruction 3

root fcb_settings lookupTable_seq15_instr3 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr3 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr3 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr3 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr3 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr3 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr3 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr3 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field176

lookupTable_seq15_instr3


Offset: 0x00000176, Width: 16b; Lookup table holds Flash command sequences 15, instruction 3

root fcb_settings field176 oneOf item 0
Type: string or number
root fcb_settings field176 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field176 oneOf item 1 value
Type: string or number
root fcb_settings field176 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field176 oneOf item 2 bitfields
Type: object

root fcb_settings field176 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field176 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field176 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field176 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field176 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field176 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field176 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr4

lookupTable_seq15_instr4


Offset: 0x00000178, Width: 16b; Lookup table holds Flash command sequences 15, instruction 4

root fcb_settings lookupTable_seq15_instr4 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr4 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr4 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr4 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr4 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr4 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr4 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr4 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field178

lookupTable_seq15_instr4


Offset: 0x00000178, Width: 16b; Lookup table holds Flash command sequences 15, instruction 4

root fcb_settings field178 oneOf item 0
Type: string or number
root fcb_settings field178 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field178 oneOf item 1 value
Type: string or number
root fcb_settings field178 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field178 oneOf item 2 bitfields
Type: object

root fcb_settings field178 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field178 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field178 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field178 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field178 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field178 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field178 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr5

lookupTable_seq15_instr5


Offset: 0x0000017A, Width: 16b; Lookup table holds Flash command sequences 15, instruction 5

root fcb_settings lookupTable_seq15_instr5 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr5 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr5 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr5 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr5 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr5 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr5 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr5 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field17A

lookupTable_seq15_instr5


Offset: 0x0000017A, Width: 16b; Lookup table holds Flash command sequences 15, instruction 5

root fcb_settings field17A oneOf item 0
Type: string or number
root fcb_settings field17A oneOf item 1
Type: object
No Additional Properties

root fcb_settings field17A oneOf item 1 value
Type: string or number
root fcb_settings field17A oneOf item 2
Type: object
No Additional Properties

root fcb_settings field17A oneOf item 2 bitfields
Type: object

root fcb_settings field17A oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field17A oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field17A oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field17A oneOf item 3
Type: object
No Additional Properties

root fcb_settings field17A oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field17A oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field17A oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr6

lookupTable_seq15_instr6


Offset: 0x0000017C, Width: 16b; Lookup table holds Flash command sequences 15, instruction 6

root fcb_settings lookupTable_seq15_instr6 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr6 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr6 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr6 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr6 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr6 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr6 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr6 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field17C

lookupTable_seq15_instr6


Offset: 0x0000017C, Width: 16b; Lookup table holds Flash command sequences 15, instruction 6

root fcb_settings field17C oneOf item 0
Type: string or number
root fcb_settings field17C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field17C oneOf item 1 value
Type: string or number
root fcb_settings field17C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field17C oneOf item 2 bitfields
Type: object

root fcb_settings field17C oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field17C oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field17C oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field17C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field17C oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field17C oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field17C oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr7

lookupTable_seq15_instr7


Offset: 0x0000017E, Width: 16b; Lookup table holds Flash command sequences 15, instruction 7

root fcb_settings lookupTable_seq15_instr7 oneOf item 0
Type: string or number
root fcb_settings lookupTable_seq15_instr7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr7 oneOf item 2 bitfields
Type: object

root fcb_settings lookupTable_seq15_instr7 oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr7 oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr7 oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lookupTable_seq15_instr7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lookupTable_seq15_instr7 oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings lookupTable_seq15_instr7 oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings lookupTable_seq15_instr7 oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field17E

lookupTable_seq15_instr7


Offset: 0x0000017E, Width: 16b; Lookup table holds Flash command sequences 15, instruction 7

root fcb_settings field17E oneOf item 0
Type: string or number
root fcb_settings field17E oneOf item 1
Type: object
No Additional Properties

root fcb_settings field17E oneOf item 1 value
Type: string or number
root fcb_settings field17E oneOf item 2
Type: object
No Additional Properties

root fcb_settings field17E oneOf item 2 bitfields
Type: object

root fcb_settings field17E oneOf item 2 bitfields OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field17E oneOf item 2 bitfields NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field17E oneOf item 2 bitfields OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings field17E oneOf item 3
Type: object
No Additional Properties

root fcb_settings field17E oneOf item 3 OPERAND

OPERAND

Type: string or number

Offset: 0b, Width: 8b, Instruction operand. Its values depends on used instruction

root fcb_settings field17E oneOf item 3 NUM_PADS

NUM_PADS

Type: string or number

Offset: 8b, Width: 2b, Number of pads used by instruction. Some instructions ignores this parameter.
- 1PAD, (0): Single mode. One pad is used.
- 2PAD, (1): Dual mode. Two pads are used.
- 4PAD, (2): Quad mode. Four pads are used.
- 8PAD, (3): Octal mode. Eight pads are used.

root fcb_settings field17E oneOf item 3 OPERATION_CODE

OPERATION_CODE

Type: string or number

Offset: 10b, Width: 6b, Instruction operation code.
- STOP, (0): Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0.
- CMDSDR, (1): Transmit command code to Flash.
- RADDRSDR, (2): Transmit row address to Flash.
- CADDRSDR, (3): Transmit column address to Flash.
- MODE1SDR, (4): Transmit mode bits to Flash.
- MODE2SDR, (5): Transmit mode bits to Flash.
- MODE4SDR, (6): Transmit mode bits to Flash.
- MODE8SDR, (7): Transmit mode bits to Flash.
- WRITESDR, (8): Transmit program data to Flash device.
- READSDR, (9): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNSDR, (10): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZSDR, (11): Transmit read or program data size (byte number) to Flash device.
- DUMMYSDR, (12): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSSDR, (13): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.
- JMPONCS, (31): Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command.
- CMDDDR, (33): Transmit command code to Flash.
- RADDRDDR, (34): Transmit row address to Flash.
- CADDRDDR, (35): Transmit column address to Flash.
- MODE1DDR, (36): Transmit mode bits to Flash.
- MODE2DDR, (37): Transmit mode bits to Flash.
- MODE4DDR, (38): Transmit mode bits to Flash.
- MODE8DDR, (39): Transmit mode bits to Flash.
- WRITEDDR, (40): Transmit program data to Flash device.
- READDDR, (41): Receive read data from Flash device. Read data is put into AHBRXBUF or IPRXFIFO.
- LEARNDDR, (42): Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase.
- DATSZDDR, (43): Transmit read or program data size (byte number) to Flash device.
- DUMMYDDR, (44): Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. numpads determines the number of pads in input mode.
- DUMMYRWDSDDR, (45): This instruction is similar to DUMMYSDR/DUMMYDDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices.

root fcb_settings lutCustomSeq_0

lutCustomSeq_0


Offset: 0x00000180, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_0 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_0 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_0 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_0 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_0 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_0 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_0 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_0 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_0 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field180

lutCustomSeq_0


Offset: 0x00000180, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field180 oneOf item 0
Type: string or number
root fcb_settings field180 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field180 oneOf item 1 value
Type: string or number
root fcb_settings field180 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field180 oneOf item 2 bitfields
Type: object

root fcb_settings field180 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field180 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field180 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field180 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field180 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field180 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field180 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_1

lutCustomSeq_1


Offset: 0x00000184, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_1 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_1 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_1 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_1 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_1 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_1 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_1 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_1 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_1 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_1 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_1 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field184

lutCustomSeq_1


Offset: 0x00000184, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field184 oneOf item 0
Type: string or number
root fcb_settings field184 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field184 oneOf item 1 value
Type: string or number
root fcb_settings field184 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field184 oneOf item 2 bitfields
Type: object

root fcb_settings field184 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field184 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field184 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field184 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field184 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field184 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field184 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_2

lutCustomSeq_2


Offset: 0x00000188, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_2 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_2 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_2 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_2 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_2 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_2 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_2 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_2 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_2 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_2 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_2 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field188

lutCustomSeq_2


Offset: 0x00000188, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field188 oneOf item 0
Type: string or number
root fcb_settings field188 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field188 oneOf item 1 value
Type: string or number
root fcb_settings field188 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field188 oneOf item 2 bitfields
Type: object

root fcb_settings field188 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field188 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field188 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field188 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field188 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field188 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field188 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_3

lutCustomSeq_3


Offset: 0x0000018C, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_3 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_3 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_3 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_3 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_3 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_3 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_3 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_3 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_3 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_3 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_3 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field18C

lutCustomSeq_3


Offset: 0x0000018C, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field18C oneOf item 0
Type: string or number
root fcb_settings field18C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field18C oneOf item 1 value
Type: string or number
root fcb_settings field18C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field18C oneOf item 2 bitfields
Type: object

root fcb_settings field18C oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field18C oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field18C oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field18C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field18C oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field18C oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field18C oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_4

lutCustomSeq_4


Offset: 0x00000190, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_4 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_4 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_4 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_4 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_4 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_4 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_4 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_4 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_4 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field190

lutCustomSeq_4


Offset: 0x00000190, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field190 oneOf item 0
Type: string or number
root fcb_settings field190 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field190 oneOf item 1 value
Type: string or number
root fcb_settings field190 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field190 oneOf item 2 bitfields
Type: object

root fcb_settings field190 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field190 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field190 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field190 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field190 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field190 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field190 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_5

lutCustomSeq_5


Offset: 0x00000194, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_5 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_5 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_5 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_5 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_5 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_5 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_5 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_5 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_5 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_5 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_5 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field194

lutCustomSeq_5


Offset: 0x00000194, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field194 oneOf item 0
Type: string or number
root fcb_settings field194 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field194 oneOf item 1 value
Type: string or number
root fcb_settings field194 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field194 oneOf item 2 bitfields
Type: object

root fcb_settings field194 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field194 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field194 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field194 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field194 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field194 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field194 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_6

lutCustomSeq_6


Offset: 0x00000198, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_6 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_6 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_6 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_6 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_6 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_6 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_6 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_6 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_6 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_6 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_6 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field198

lutCustomSeq_6


Offset: 0x00000198, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field198 oneOf item 0
Type: string or number
root fcb_settings field198 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field198 oneOf item 1 value
Type: string or number
root fcb_settings field198 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field198 oneOf item 2 bitfields
Type: object

root fcb_settings field198 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field198 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field198 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field198 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field198 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field198 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field198 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_7

lutCustomSeq_7


Offset: 0x0000019C, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_7 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_7 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_7 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_7 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_7 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_7 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_7 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_7 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_7 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_7 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_7 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field19C

lutCustomSeq_7


Offset: 0x0000019C, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field19C oneOf item 0
Type: string or number
root fcb_settings field19C oneOf item 1
Type: object
No Additional Properties

root fcb_settings field19C oneOf item 1 value
Type: string or number
root fcb_settings field19C oneOf item 2
Type: object
No Additional Properties

root fcb_settings field19C oneOf item 2 bitfields
Type: object

root fcb_settings field19C oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field19C oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field19C oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field19C oneOf item 3
Type: object
No Additional Properties

root fcb_settings field19C oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field19C oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field19C oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_8

lutCustomSeq_8


Offset: 0x000001A0, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_8 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_8 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_8 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_8 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_8 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_8 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_8 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_8 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_8 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field1A0

lutCustomSeq_8


Offset: 0x000001A0, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field1A0 oneOf item 0
Type: string or number
root fcb_settings field1A0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1A0 oneOf item 1 value
Type: string or number
root fcb_settings field1A0 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field1A0 oneOf item 2 bitfields
Type: object

root fcb_settings field1A0 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1A0 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1A0 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field1A0 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field1A0 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1A0 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1A0 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_9

lutCustomSeq_9


Offset: 0x000001A4, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_9 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_9 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_9 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_9 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_9 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_9 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_9 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_9 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_9 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_9 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_9 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_9 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field1A4

lutCustomSeq_9


Offset: 0x000001A4, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field1A4 oneOf item 0
Type: string or number
root fcb_settings field1A4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1A4 oneOf item 1 value
Type: string or number
root fcb_settings field1A4 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field1A4 oneOf item 2 bitfields
Type: object

root fcb_settings field1A4 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1A4 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1A4 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field1A4 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field1A4 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1A4 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1A4 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_10

lutCustomSeq_10


Offset: 0x000001A8, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_10 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_10 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_10 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_10 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_10 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_10 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_10 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_10 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_10 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_10 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_10 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_10 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field1A8

lutCustomSeq_10


Offset: 0x000001A8, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field1A8 oneOf item 0
Type: string or number
root fcb_settings field1A8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1A8 oneOf item 1 value
Type: string or number
root fcb_settings field1A8 oneOf item 2
Type: object
No Additional Properties

root fcb_settings field1A8 oneOf item 2 bitfields
Type: object

root fcb_settings field1A8 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1A8 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1A8 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field1A8 oneOf item 3
Type: object
No Additional Properties

root fcb_settings field1A8 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1A8 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1A8 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings lutCustomSeq_11

lutCustomSeq_11


Offset: 0x000001AC, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings lutCustomSeq_11 oneOf item 0
Type: string or number
root fcb_settings lutCustomSeq_11 oneOf item 1
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_11 oneOf item 1 value
Type: string or number
root fcb_settings lutCustomSeq_11 oneOf item 2
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_11 oneOf item 2 bitfields
Type: object

root fcb_settings lutCustomSeq_11 oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_11 oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_11 oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings lutCustomSeq_11 oneOf item 3
Type: object
No Additional Properties

root fcb_settings lutCustomSeq_11 oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings lutCustomSeq_11 oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings lutCustomSeq_11 oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings field1AC

lutCustomSeq_11


Offset: 0x000001AC, Width: 32b; [0x180-0x1af] Customizable LUT Sequences

root fcb_settings field1AC oneOf item 0
Type: string or number
root fcb_settings field1AC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1AC oneOf item 1 value
Type: string or number
root fcb_settings field1AC oneOf item 2
Type: object
No Additional Properties

root fcb_settings field1AC oneOf item 2 bitfields
Type: object

root fcb_settings field1AC oneOf item 2 bitfields seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1AC oneOf item 2 bitfields seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1AC oneOf item 2 bitfields reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A
root fcb_settings field1AC oneOf item 3
Type: object
No Additional Properties

root fcb_settings field1AC oneOf item 3 seqNum

seqNum

Type: string or number

Offset: 0b, Width: 8b, Sequence Number, valid number: 1-16

root fcb_settings field1AC oneOf item 3 seqId

seqId

Type: string or number

Offset: 8b, Width: 8b, Sequence Index, valid number: 0-15

root fcb_settings field1AC oneOf item 3 reserved

reserved

Type: string or number

Offset: 16b, Width: 16b, N/A

root fcb_settings reserved4_0

reserved4_0


Offset: 0x000001B0, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings reserved4_0 oneOf item 0
Type: string or number
root fcb_settings reserved4_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved4_0 oneOf item 1 value
Type: string or number

root fcb_settings field1B0

reserved4_0


Offset: 0x000001B0, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings field1B0 oneOf item 0
Type: string or number
root fcb_settings field1B0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1B0 oneOf item 1 value
Type: string or number

root fcb_settings reserved4_1

reserved4_1


Offset: 0x000001B4, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings reserved4_1 oneOf item 0
Type: string or number
root fcb_settings reserved4_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved4_1 oneOf item 1 value
Type: string or number

root fcb_settings field1B4

reserved4_1


Offset: 0x000001B4, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings field1B4 oneOf item 0
Type: string or number
root fcb_settings field1B4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1B4 oneOf item 1 value
Type: string or number

root fcb_settings reserved4_2

reserved4_2


Offset: 0x000001B8, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings reserved4_2 oneOf item 0
Type: string or number
root fcb_settings reserved4_2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved4_2 oneOf item 1 value
Type: string or number

root fcb_settings field1B8

reserved4_2


Offset: 0x000001B8, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings field1B8 oneOf item 0
Type: string or number
root fcb_settings field1B8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1B8 oneOf item 1 value
Type: string or number

root fcb_settings reserved4_3

reserved4_3


Offset: 0x000001BC, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings reserved4_3 oneOf item 0
Type: string or number
root fcb_settings reserved4_3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved4_3 oneOf item 1 value
Type: string or number

root fcb_settings field1BC

reserved4_3


Offset: 0x000001BC, Width: 32b; [0x1b0-0x1bf] Reserved for future use

root fcb_settings field1BC oneOf item 0
Type: string or number
root fcb_settings field1BC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1BC oneOf item 1 value
Type: string or number

root fcb_settings pageSize

pageSize


Offset: 0x000001C0, Width: 32b; Page size of Serial NOR

root fcb_settings pageSize oneOf item 0
Type: string or number
root fcb_settings pageSize oneOf item 1
Type: object
No Additional Properties

root fcb_settings pageSize oneOf item 1 value
Type: string or number

root fcb_settings field1C0

pageSize


Offset: 0x000001C0, Width: 32b; Page size of Serial NOR

root fcb_settings field1C0 oneOf item 0
Type: string or number
root fcb_settings field1C0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1C0 oneOf item 1 value
Type: string or number

root fcb_settings sectorSize

sectorSize


Offset: 0x000001C4, Width: 32b; Sector size of Serial NOR

root fcb_settings sectorSize oneOf item 0
Type: string or number
root fcb_settings sectorSize oneOf item 1
Type: object
No Additional Properties

root fcb_settings sectorSize oneOf item 1 value
Type: string or number

root fcb_settings field1C4

sectorSize


Offset: 0x000001C4, Width: 32b; Sector size of Serial NOR

root fcb_settings field1C4 oneOf item 0
Type: string or number
root fcb_settings field1C4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1C4 oneOf item 1 value
Type: string or number

root fcb_settings ipcmdSerialClkFreq

ipcmdSerialClkFreq


Offset: 0x000001C8, Width: 8b; Clock frequency for IP command

root fcb_settings ipcmdSerialClkFreq oneOf item 0
Type: string or number
root fcb_settings ipcmdSerialClkFreq oneOf item 1
Type: object
No Additional Properties

root fcb_settings ipcmdSerialClkFreq oneOf item 1 value
Type: string or number

root fcb_settings field1C8

ipcmdSerialClkFreq


Offset: 0x000001C8, Width: 8b; Clock frequency for IP command

root fcb_settings field1C8 oneOf item 0
Type: string or number
root fcb_settings field1C8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1C8 oneOf item 1 value
Type: string or number

root fcb_settings isUniformBlockSize

isUniformBlockSize


Offset: 0x000001C9, Width: 8b; Sector/Block size is the same

root fcb_settings isUniformBlockSize oneOf item 0
Type: string or number
root fcb_settings isUniformBlockSize oneOf item 1
Type: object
No Additional Properties

root fcb_settings isUniformBlockSize oneOf item 1 value
Type: string or number

root fcb_settings field1C9

isUniformBlockSize


Offset: 0x000001C9, Width: 8b; Sector/Block size is the same

root fcb_settings field1C9 oneOf item 0
Type: string or number
root fcb_settings field1C9 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1C9 oneOf item 1 value
Type: string or number

root fcb_settings isDataOrderSwapped

isDataOrderSwapped


Offset: 0x000001CA, Width: 8b; Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)

root fcb_settings isDataOrderSwapped oneOf item 0
Type: string or number
root fcb_settings isDataOrderSwapped oneOf item 1
Type: object
No Additional Properties

root fcb_settings isDataOrderSwapped oneOf item 1 value
Type: string or number

root fcb_settings field1CA

isDataOrderSwapped


Offset: 0x000001CA, Width: 8b; Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)

root fcb_settings field1CA oneOf item 0
Type: string or number
root fcb_settings field1CA oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1CA oneOf item 1 value
Type: string or number

root fcb_settings reserved0_0

reserved0_0


Offset: 0x000001CB, Width: 8b; Reserved for future use

root fcb_settings reserved0_0 oneOf item 0
Type: string or number
root fcb_settings reserved0_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserved0_0 oneOf item 1 value
Type: string or number

root fcb_settings field1CB

reserved0_0


Offset: 0x000001CB, Width: 8b; Reserved for future use

root fcb_settings field1CB oneOf item 0
Type: string or number
root fcb_settings field1CB oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1CB oneOf item 1 value
Type: string or number

root fcb_settings serialNorType

serialNorType


Offset: 0x000001CC, Width: 8b; Serial NOR Flash type: 0/1/2/3

root fcb_settings serialNorType oneOf item 0
Type: string or number
root fcb_settings serialNorType oneOf item 1
Type: object
No Additional Properties

root fcb_settings serialNorType oneOf item 1 value
Type: string or number

root fcb_settings field1CC

serialNorType


Offset: 0x000001CC, Width: 8b; Serial NOR Flash type: 0/1/2/3

root fcb_settings field1CC oneOf item 0
Type: string or number
root fcb_settings field1CC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1CC oneOf item 1 value
Type: string or number

root fcb_settings needExitNoCmdMode

needExitNoCmdMode


Offset: 0x000001CD, Width: 8b; Need to exit NoCmd mode before other IP command

root fcb_settings needExitNoCmdMode oneOf item 0
Type: string or number
root fcb_settings needExitNoCmdMode oneOf item 1
Type: object
No Additional Properties

root fcb_settings needExitNoCmdMode oneOf item 1 value
Type: string or number

root fcb_settings field1CD

needExitNoCmdMode


Offset: 0x000001CD, Width: 8b; Need to exit NoCmd mode before other IP command

root fcb_settings field1CD oneOf item 0
Type: string or number
root fcb_settings field1CD oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1CD oneOf item 1 value
Type: string or number

root fcb_settings halfClkForNonReadCmd

halfClkForNonReadCmd


Offset: 0x000001CE, Width: 8b; Half the Serial Clock for non-read command: true/false

root fcb_settings halfClkForNonReadCmd oneOf item 0
Type: string or number
root fcb_settings halfClkForNonReadCmd oneOf item 1
Type: object
No Additional Properties

root fcb_settings halfClkForNonReadCmd oneOf item 1 value
Type: string or number

root fcb_settings field1CE

halfClkForNonReadCmd


Offset: 0x000001CE, Width: 8b; Half the Serial Clock for non-read command: true/false

root fcb_settings field1CE oneOf item 0
Type: string or number
root fcb_settings field1CE oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1CE oneOf item 1 value
Type: string or number

root fcb_settings needRestoreNoCmdMode

needRestoreNoCmdMode


Offset: 0x000001CF, Width: 8b; Need to Restore NoCmd mode after IP command execution

root fcb_settings needRestoreNoCmdMode oneOf item 0
Type: string or number
root fcb_settings needRestoreNoCmdMode oneOf item 1
Type: object
No Additional Properties

root fcb_settings needRestoreNoCmdMode oneOf item 1 value
Type: string or number

root fcb_settings field1CF

needRestoreNoCmdMode


Offset: 0x000001CF, Width: 8b; Need to Restore NoCmd mode after IP command execution

root fcb_settings field1CF oneOf item 0
Type: string or number
root fcb_settings field1CF oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1CF oneOf item 1 value
Type: string or number

root fcb_settings blockSize

blockSize


Offset: 0x000001D0, Width: 32b; Block size

root fcb_settings blockSize oneOf item 0
Type: string or number
root fcb_settings blockSize oneOf item 1
Type: object
No Additional Properties

root fcb_settings blockSize oneOf item 1 value
Type: string or number

root fcb_settings field1D0

blockSize


Offset: 0x000001D0, Width: 32b; Block size

root fcb_settings field1D0 oneOf item 0
Type: string or number
root fcb_settings field1D0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1D0 oneOf item 1 value
Type: string or number

root fcb_settings flashStateCtx

flashStateCtx


Offset: 0x000001D4, Width: 32b; Flash State Context

root fcb_settings flashStateCtx oneOf item 0
Type: string or number
root fcb_settings flashStateCtx oneOf item 1
Type: object
No Additional Properties

root fcb_settings flashStateCtx oneOf item 1 value
Type: string or number

root fcb_settings field1D4

flashStateCtx


Offset: 0x000001D4, Width: 32b; Flash State Context

root fcb_settings field1D4 oneOf item 0
Type: string or number
root fcb_settings field1D4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1D4 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_0

reserve2_0


Offset: 0x000001D8, Width: 32b; Reserved for future use

root fcb_settings reserve2_0 oneOf item 0
Type: string or number
root fcb_settings reserve2_0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_0 oneOf item 1 value
Type: string or number

root fcb_settings field1D8

reserve2_0


Offset: 0x000001D8, Width: 32b; Reserved for future use

root fcb_settings field1D8 oneOf item 0
Type: string or number
root fcb_settings field1D8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1D8 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_1

reserve2_1


Offset: 0x000001DC, Width: 32b; Reserved for future use

root fcb_settings reserve2_1 oneOf item 0
Type: string or number
root fcb_settings reserve2_1 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_1 oneOf item 1 value
Type: string or number

root fcb_settings field1DC

reserve2_1


Offset: 0x000001DC, Width: 32b; Reserved for future use

root fcb_settings field1DC oneOf item 0
Type: string or number
root fcb_settings field1DC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1DC oneOf item 1 value
Type: string or number

root fcb_settings reserve2_2

reserve2_2


Offset: 0x000001E0, Width: 32b; Reserved for future use

root fcb_settings reserve2_2 oneOf item 0
Type: string or number
root fcb_settings reserve2_2 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_2 oneOf item 1 value
Type: string or number

root fcb_settings field1E0

reserve2_2


Offset: 0x000001E0, Width: 32b; Reserved for future use

root fcb_settings field1E0 oneOf item 0
Type: string or number
root fcb_settings field1E0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1E0 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_3

reserve2_3


Offset: 0x000001E4, Width: 32b; Reserved for future use

root fcb_settings reserve2_3 oneOf item 0
Type: string or number
root fcb_settings reserve2_3 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_3 oneOf item 1 value
Type: string or number

root fcb_settings field1E4

reserve2_3


Offset: 0x000001E4, Width: 32b; Reserved for future use

root fcb_settings field1E4 oneOf item 0
Type: string or number
root fcb_settings field1E4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1E4 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_4

reserve2_4


Offset: 0x000001E8, Width: 32b; Reserved for future use

root fcb_settings reserve2_4 oneOf item 0
Type: string or number
root fcb_settings reserve2_4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_4 oneOf item 1 value
Type: string or number

root fcb_settings field1E8

reserve2_4


Offset: 0x000001E8, Width: 32b; Reserved for future use

root fcb_settings field1E8 oneOf item 0
Type: string or number
root fcb_settings field1E8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1E8 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_5

reserve2_5


Offset: 0x000001EC, Width: 32b; Reserved for future use

root fcb_settings reserve2_5 oneOf item 0
Type: string or number
root fcb_settings reserve2_5 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_5 oneOf item 1 value
Type: string or number

root fcb_settings field1EC

reserve2_5


Offset: 0x000001EC, Width: 32b; Reserved for future use

root fcb_settings field1EC oneOf item 0
Type: string or number
root fcb_settings field1EC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1EC oneOf item 1 value
Type: string or number

root fcb_settings reserve2_6

reserve2_6


Offset: 0x000001F0, Width: 32b; Reserved for future use

root fcb_settings reserve2_6 oneOf item 0
Type: string or number
root fcb_settings reserve2_6 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_6 oneOf item 1 value
Type: string or number

root fcb_settings field1F0

reserve2_6


Offset: 0x000001F0, Width: 32b; Reserved for future use

root fcb_settings field1F0 oneOf item 0
Type: string or number
root fcb_settings field1F0 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1F0 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_7

reserve2_7


Offset: 0x000001F4, Width: 32b; Reserved for future use

root fcb_settings reserve2_7 oneOf item 0
Type: string or number
root fcb_settings reserve2_7 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_7 oneOf item 1 value
Type: string or number

root fcb_settings field1F4

reserve2_7


Offset: 0x000001F4, Width: 32b; Reserved for future use

root fcb_settings field1F4 oneOf item 0
Type: string or number
root fcb_settings field1F4 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1F4 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_8

reserve2_8


Offset: 0x000001F8, Width: 32b; Reserved for future use

root fcb_settings reserve2_8 oneOf item 0
Type: string or number
root fcb_settings reserve2_8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_8 oneOf item 1 value
Type: string or number

root fcb_settings field1F8

reserve2_8


Offset: 0x000001F8, Width: 32b; Reserved for future use

root fcb_settings field1F8 oneOf item 0
Type: string or number
root fcb_settings field1F8 oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1F8 oneOf item 1 value
Type: string or number

root fcb_settings reserve2_9

reserve2_9


Offset: 0x000001FC, Width: 32b; Reserved for future use

root fcb_settings reserve2_9 oneOf item 0
Type: string or number
root fcb_settings reserve2_9 oneOf item 1
Type: object
No Additional Properties

root fcb_settings reserve2_9 oneOf item 1 value
Type: string or number

root fcb_settings field1FC

reserve2_9


Offset: 0x000001FC, Width: 32b; Reserved for future use

root fcb_settings field1FC oneOf item 0
Type: string or number
root fcb_settings field1FC oneOf item 1
Type: object
No Additional Properties

root fcb_settings field1FC oneOf item 1 value
Type: string or number