NXP chip family identifier.
Revision of silicon. The 'latest' name, means most current revision.
Specify type of memory used by XMCD description.
Specify type of configuration used by XMCD description.
Offset: 0x00000000, Width: 32b; XMCD Header
Offset: 0b, Width: 12b, Configuration block size including XMCD header itself
Offset: 12b, Width: 4b, Configuration block type: 0 - Simplified, 1 - Full
- XMCDCONFIGBLOCKTYPESIMPLIFIED, (0): Simplified configuration block type
- XMCDCONFIGBLOCKTYPEFULL, (1): Full configuration block type
Offset: 16b, Width: 4b, SoC defined instances
Offset: 20b, Width: 4b, Memory interface: 0 - FlexSPI, 1 - SEMC
- XMCDMEMORYINTERFACEFLEXSPI, (0): FlexSPI memory interface
- XMCDMEMORYINTERFACESEMC, (1): SEMC memory interface
Offset: 24b, Width: 4b, Version, fixed value 0x0
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0b, Width: 12b, Configuration block size including XMCD header itself
Offset: 12b, Width: 4b, Configuration block type: 0 - Simplified, 1 - Full
- XMCDCONFIGBLOCKTYPESIMPLIFIED, (0): Simplified configuration block type
- XMCDCONFIGBLOCKTYPEFULL, (1): Full configuration block type
Offset: 16b, Width: 4b, SoC defined instances
Offset: 20b, Width: 4b, Memory interface: 0 - FlexSPI, 1 - SEMC
- XMCDMEMORYINTERFACEFLEXSPI, (0): FlexSPI memory interface
- XMCDMEMORYINTERFACESEMC, (1): SEMC memory interface
Offset: 24b, Width: 4b, Version, fixed value 0x0
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0x00000000, Width: 32b; XMCD Header
Offset: 0b, Width: 12b, Configuration block size including XMCD header itself
Offset: 12b, Width: 4b, Configuration block type: 0 - Simplified, 1 - Full
- XMCDCONFIGBLOCKTYPESIMPLIFIED, (0): Simplified configuration block type
- XMCDCONFIGBLOCKTYPEFULL, (1): Full configuration block type
Offset: 16b, Width: 4b, SoC defined instances
Offset: 20b, Width: 4b, Memory interface: 0 - FlexSPI, 1 - SEMC
- XMCDMEMORYINTERFACEFLEXSPI, (0): FlexSPI memory interface
- XMCDMEMORYINTERFACESEMC, (1): SEMC memory interface
Offset: 24b, Width: 4b, Version, fixed value 0x0
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0b, Width: 12b, Configuration block size including XMCD header itself
Offset: 12b, Width: 4b, Configuration block type: 0 - Simplified, 1 - Full
- XMCDCONFIGBLOCKTYPESIMPLIFIED, (0): Simplified configuration block type
- XMCDCONFIGBLOCKTYPEFULL, (1): Full configuration block type
Offset: 16b, Width: 4b, SoC defined instances
Offset: 20b, Width: 4b, Memory interface: 0 - FlexSPI, 1 - SEMC
- XMCDMEMORYINTERFACEFLEXSPI, (0): FlexSPI memory interface
- XMCDMEMORYINTERFACESEMC, (1): SEMC memory interface
Offset: 24b, Width: 4b, Version, fixed value 0x0
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0x00000004, Width: 8b; Fixed to 0xA1
Offset: 0x00000004, Width: 8b; Fixed to 0xA1
Offset: 0x00000005, Width: 8b; Set to 1 for this implementation
Offset: 0x00000005, Width: 8b; Set to 1 for this implementation
Offset: 0x00000006, Width: 8b; Simplified - 0x00, Full - 0xFF - Must be 0xFF in this case
Offset: 0b, Width: 8b, Config option
- XMCDSEMCSDRAMCONFIGFULL, (0): Full configuration. Must configure all fields.
Offset: 0b, Width: 8b, Config option
- XMCDSEMCSDRAMCONFIGFULL, (0): Full configuration. Must configure all fields.
Offset: 0x00000006, Width: 8b; Simplified - 0x00, Full - 0xFF - Must be 0xFF in this case
Offset: 0b, Width: 8b, Config option
- XMCDSEMCSDRAMCONFIGFULL, (0): Full configuration. Must configure all fields.
Offset: 0b, Width: 8b, Config option
- XMCDSEMCSDRAMCONFIGFULL, (0): Full configuration. Must configure all fields.
Offset: 0x00000007, Width: 8b; Set the working frequency in the unit of MHz
Offset: 0x00000007, Width: 8b; Set the working frequency in the unit of MHz
Offset: 0x00000008, Width: 32b; Set the memory size of SDRAM CS0 in the unit of kilobytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x00000008, Width: 32b; Set the memory size of SDRAM CS0 in the unit of kilobytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x0000000C, Width: 8b; Port size of SDRAM: 0 - 8-bit, 1 - 16-bit, 2 - 32-bit
Offset: 0b, Width: 8b, Port size of SDRAM
- XMCDSEMCSDRAMPORTSIZE8BIT, (0): 8-bit
- XMCDSEMCSDRAMPORTSIZE16BIT, (1): 16-bit
- XMCDSEMCSDRAMPORTSIZE32BIT, (2): 32-bit
Offset: 0b, Width: 8b, Port size of SDRAM
- XMCDSEMCSDRAMPORTSIZE8BIT, (0): 8-bit
- XMCDSEMCSDRAMPORTSIZE16BIT, (1): 16-bit
- XMCDSEMCSDRAMPORTSIZE32BIT, (2): 32-bit
Offset: 0x0000000C, Width: 8b; Port size of SDRAM: 0 - 8-bit, 1 - 16-bit, 2 - 32-bit
Offset: 0b, Width: 8b, Port size of SDRAM
- XMCDSEMCSDRAMPORTSIZE8BIT, (0): 8-bit
- XMCDSEMCSDRAMPORTSIZE16BIT, (1): 16-bit
- XMCDSEMCSDRAMPORTSIZE32BIT, (2): 32-bit
Offset: 0b, Width: 8b, Port size of SDRAM
- XMCDSEMCSDRAMPORTSIZE8BIT, (0): 8-bit
- XMCDSEMCSDRAMPORTSIZE16BIT, (1): 16-bit
- XMCDSEMCSDRAMPORTSIZE32BIT, (2): 32-bit
Offset: 0x0000000D, Width: 8b; Pull config of the SDRAM GPIO pin: 0 - Forbidden, 1 - Pull up, 2 - Pull down, 3 - No pull, Others - Invalid value
Offset: 0x0000000D, Width: 8b; Pull config of the SDRAM GPIO pin: 0 - Forbidden, 1 - Pull up, 2 - Pull down, 3 - No pull, Others - Invalid value
Offset: 0x0000000E, Width: 8b; Driver config of SDRAM GPIO pin: 0 - High driver, 1 - Normal driver, Others - Invalid value
Offset: 0b, Width: 8b, Driver config of SDRAM GPIO pin
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHHIGH, (0): High driver
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHNORM, (1): Normal driver
Offset: 0b, Width: 8b, Driver config of SDRAM GPIO pin
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHHIGH, (0): High driver
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHNORM, (1): Normal driver
Offset: 0x0000000E, Width: 8b; Driver config of SDRAM GPIO pin: 0 - High driver, 1 - Normal driver, Others - Invalid value
Offset: 0b, Width: 8b, Driver config of SDRAM GPIO pin
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHHIGH, (0): High driver
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHNORM, (1): Normal driver
Offset: 0b, Width: 8b, Driver config of SDRAM GPIO pin
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHHIGH, (0): High driver
- XMCDSEMCSDRAMPINCONFIGDRIVESTRENGTHNORM, (1): Normal driver
Offset: 0x0000000F, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXRDYCS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXRDYCS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXRDY_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXRDYCS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXRDYCS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXRDY_CS3, (3): SDRAM CS3
Offset: 0x0000000F, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXRDYCS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXRDYCS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXRDY_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXRDYCS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXRDYCS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXRDY_CS3, (3): SDRAM CS3
Offset: 0x00000010, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX0CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX0CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX0_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX0CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX0CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX0_CS3, (3): SDRAM CS3
Offset: 0x00000010, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX0CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX0CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX0_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX0CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX0CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX0_CS3, (3): SDRAM CS3
Offset: 0x00000011, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX1CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX1CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX1_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX1CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX1CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX1_CS3, (3): SDRAM CS3
Offset: 0x00000011, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX1CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX1CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX1_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX1CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX1CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX1_CS3, (3): SDRAM CS3
Offset: 0x00000012, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX2CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX2CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX2_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX2CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX2CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX2_CS3, (3): SDRAM CS3
Offset: 0x00000012, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX2CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX2CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX2_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX2CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX2CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX2_CS3, (3): SDRAM CS3
Offset: 0x00000013, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX3CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX3CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX3_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX3CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX3CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX3_CS3, (3): SDRAM CS3
Offset: 0x00000013, Width: 8b; SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX3CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX3CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX3_CS3, (3): SDRAM CS3
Offset: 0b, Width: 8b, SDRAM CSn device selection
- XMCDSEMCSDRAMMUXCSX3CS1, (1): SDRAM CS1
- XMCDSEMCSDRAMMUXCSX3CS2, (2): SDRAM CS2
- XMCDSEMCSDRAMMUXCSX3_CS3, (3): SDRAM CS3
Offset: 0x00000014, Width: 8b; Bank numbers of SDRAM device: 0 - 4 banks, 1 - 2 banks, Others - Invalid value
Offset: 0b, Width: 8b, Bank numbers of SDRAM device
- XMCDSEMCSDRAMBANK4, (0): 4 banks
- XMCDSEMCSDRAMBANK2, (1): 2 banks
Offset: 0b, Width: 8b, Bank numbers of SDRAM device
- XMCDSEMCSDRAMBANK4, (0): 4 banks
- XMCDSEMCSDRAMBANK2, (1): 2 banks
Offset: 0x00000014, Width: 8b; Bank numbers of SDRAM device: 0 - 4 banks, 1 - 2 banks, Others - Invalid value
Offset: 0b, Width: 8b, Bank numbers of SDRAM device
- XMCDSEMCSDRAMBANK4, (0): 4 banks
- XMCDSEMCSDRAMBANK2, (1): 2 banks
Offset: 0b, Width: 8b, Bank numbers of SDRAM device
- XMCDSEMCSDRAMBANK4, (0): 4 banks
- XMCDSEMCSDRAMBANK2, (1): 2 banks
Offset: 0x00000015, Width: 8b; Burst length: 0 - 1, 1 - 2, 2 - 4, 3 - 8, Others - Invalid value
Offset: 0x00000015, Width: 8b; Burst length: 0 - 1, 1 - 2, 2 - 4, 3 - 8, Others - Invalid value
Offset: 0x00000016, Width: 8b; Column address bit number: 0 - 12 bit, 1 - 11 bit, 2 - 10 bit, 3 - 9 bit, 4 - 8 bit, Others - Invalid value
Offset: 0b, Width: 8b, Column address bit number
- XMCDSEMCSDRAMCOLADDRBITNUM12, (0): 12 bit
- XMCDSEMCSDRAMCOLADDRBITNUM11, (1): 11 bit
- XMCDSEMCSDRAMCOLADDRBITNUM10, (2): 10 bit
- XMCDSEMCSDRAMCOLADDRBITNUM9, (3): 9 bit
- XMCDSEMCSDRAMCOLADDRBITNUM_8, (4): 8 bit
Offset: 0b, Width: 8b, Column address bit number
- XMCDSEMCSDRAMCOLADDRBITNUM12, (0): 12 bit
- XMCDSEMCSDRAMCOLADDRBITNUM11, (1): 11 bit
- XMCDSEMCSDRAMCOLADDRBITNUM10, (2): 10 bit
- XMCDSEMCSDRAMCOLADDRBITNUM9, (3): 9 bit
- XMCDSEMCSDRAMCOLADDRBITNUM_8, (4): 8 bit
Offset: 0x00000016, Width: 8b; Column address bit number: 0 - 12 bit, 1 - 11 bit, 2 - 10 bit, 3 - 9 bit, 4 - 8 bit, Others - Invalid value
Offset: 0b, Width: 8b, Column address bit number
- XMCDSEMCSDRAMCOLADDRBITNUM12, (0): 12 bit
- XMCDSEMCSDRAMCOLADDRBITNUM11, (1): 11 bit
- XMCDSEMCSDRAMCOLADDRBITNUM10, (2): 10 bit
- XMCDSEMCSDRAMCOLADDRBITNUM9, (3): 9 bit
- XMCDSEMCSDRAMCOLADDRBITNUM_8, (4): 8 bit
Offset: 0b, Width: 8b, Column address bit number
- XMCDSEMCSDRAMCOLADDRBITNUM12, (0): 12 bit
- XMCDSEMCSDRAMCOLADDRBITNUM11, (1): 11 bit
- XMCDSEMCSDRAMCOLADDRBITNUM10, (2): 10 bit
- XMCDSEMCSDRAMCOLADDRBITNUM9, (3): 9 bit
- XMCDSEMCSDRAMCOLADDRBITNUM_8, (4): 8 bit
Offset: 0x00000017, Width: 8b; CAS Latency: 1 - 1, 2 - 2, 3 - 3, Others - Invalid value
Offset: 0b, Width: 8b, CAS Latency
- XMCDSEMCSDRAMCASLATENCY1, (1): 1
- XMCDSEMCSDRAMCASLATENCY2, (2): 2
- XMCDSEMCSDRAMCASLATENCY_3, (3): 3
Offset: 0b, Width: 8b, CAS Latency
- XMCDSEMCSDRAMCASLATENCY1, (1): 1
- XMCDSEMCSDRAMCASLATENCY2, (2): 2
- XMCDSEMCSDRAMCASLATENCY_3, (3): 3
Offset: 0x00000017, Width: 8b; CAS Latency: 1 - 1, 2 - 2, 3 - 3, Others - Invalid value
Offset: 0b, Width: 8b, CAS Latency
- XMCDSEMCSDRAMCASLATENCY1, (1): 1
- XMCDSEMCSDRAMCASLATENCY2, (2): 2
- XMCDSEMCSDRAMCASLATENCY_3, (3): 3
Offset: 0b, Width: 8b, CAS Latency
- XMCDSEMCSDRAMCASLATENCY1, (1): 1
- XMCDSEMCSDRAMCASLATENCY2, (2): 2
- XMCDSEMCSDRAMCASLATENCY_3, (3): 3
Offset: 0x00000018, Width: 8b; Write recovery time in unit of nanosecond. This could help to meet tWR timing requirement by the SDRAM device.
Offset: 0x00000018, Width: 8b; Write recovery time in unit of nanosecond. This could help to meet tWR timing requirement by the SDRAM device.
Offset: 0x00000019, Width: 8b; Refresh recovery time in unit of nanosecond. This could help to meet tRFC timing requirement by the SDRAM device.
Offset: 0x00000019, Width: 8b; Refresh recovery time in unit of nanosecond. This could help to meet tRFC timing requirement by the SDRAM device.
Offset: 0x0000001A, Width: 8b; Act to read/write wait time in unit of nanosecond. This could help to meet tRCD timing requirement by the SDRAM device.
Offset: 0x0000001A, Width: 8b; Act to read/write wait time in unit of nanosecond. This could help to meet tRCD timing requirement by the SDRAM device.
Offset: 0x0000001B, Width: 8b; Precharge to active wait time in unit of nanosecond. This could help to meet tRP timing requirement by SDRAM device.
Offset: 0x0000001B, Width: 8b; Precharge to active wait time in unit of nanosecond. This could help to meet tRP timing requirement by SDRAM device.
Offset: 0x0000001C, Width: 8b; Active to active wait time between two different banks in unit of nanosecond. This could help to meet tRRD timing requirement by the SDRAM device.
Offset: 0x0000001C, Width: 8b; Active to active wait time between two different banks in unit of nanosecond. This could help to meet tRRD timing requirement by the SDRAM device.
Offset: 0x0000001D, Width: 8b; Auto refresh to auto refresh wait time in unit of nanosecond. This could help to meet tRFC timing requirement by the SDRAM device.
Offset: 0x0000001D, Width: 8b; Auto refresh to auto refresh wait time in unit of nanosecond. This could help to meet tRFC timing requirement by the SDRAM device.
Offset: 0x0000001E, Width: 8b; Self refresh recovery time in unit of nanosecond. This could help to meet tXSR timing requirement by the SDRAM device.
Offset: 0x0000001E, Width: 8b; Self refresh recovery time in unit of nanosecond. This could help to meet tXSR timing requirement by the SDRAM device.
Offset: 0x0000001F, Width: 8b; ACT to Precharge minimum time in unit of nanosecond. This could help to meet tRAS(max) timing requirement by the SDRAM device.
Offset: 0x0000001F, Width: 8b; ACT to Precharge minimum time in unit of nanosecond. This could help to meet tRAS(max) timing requirement by the SDRAM device.
Offset: 0x00000020, Width: 32b; ACT to Precharge maximum time in unit of nanosecond. This could help to meet tRAS(max) timing requirement by the SDRAM device.
Offset: 0x00000020, Width: 32b; ACT to Precharge maximum time in unit of nanosecond. This could help to meet tRAS(max) timing requirement by the SDRAM device.
Offset: 0x00000024, Width: 32b; Refresh timer period in unit of nanosecond. Set to (tREF(ms) * 1000000/rows) value.
Offset: 0x00000024, Width: 32b; Refresh timer period in unit of nanosecond. Set to (tREF(ms) * 1000000/rows) value.
Offset: 0x00000028, Width: 32b; Define the specific mode of operation of SDRAM. Set to the value required by SDRAM device.
Offset: 0x00000028, Width: 32b; Define the specific mode of operation of SDRAM. Set to the value required by SDRAM device.
Offset: 0x0000002C, Width: 32b; Base address of SDRAM CS0. Range: 0x80000000~0xDFFFFFFF.
Offset: 0x0000002C, Width: 32b; Base address of SDRAM CS0. Range: 0x80000000~0xDFFFFFFF.
Offset: 0x00000030, Width: 32b; Base address of SDRAM CS1. Range: 0x80000000~0xDFFFFFFF. If CS1 is not being used, set the address to 0.
Offset: 0x00000030, Width: 32b; Base address of SDRAM CS1. Range: 0x80000000~0xDFFFFFFF. If CS1 is not being used, set the address to 0.
Offset: 0x00000034, Width: 32b; Base address of SDRAM CS2. Range: 0x80000000~0xDFFFFFFF. If CS2 is not being used, set the address to 0.
Offset: 0x00000034, Width: 32b; Base address of SDRAM CS2. Range: 0x80000000~0xDFFFFFFF. If CS2 is not being used, set the address to 0.
Offset: 0x00000038, Width: 32b; Base address of SDRAM CS3. Range: 0x80000000~0xDFFFFFFF. If CS3 is not being used, set the address to 0.
Offset: 0x00000038, Width: 32b; Base address of SDRAM CS3. Range: 0x80000000~0xDFFFFFFF. If CS3 is not being used, set the address to 0.
Offset: 0x0000003C, Width: 32b; Set the memory size of SDRAM CS1 in unit of kbytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x0000003C, Width: 32b; Set the memory size of SDRAM CS1 in unit of kbytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x00000040, Width: 32b; Set the memory size of SDRAM CS2 in unit of kbytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x00000040, Width: 32b; Set the memory size of SDRAM CS2 in unit of kbytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x00000044, Width: 32b; Set the memory size of SDRAM CS3 in unit of kbytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.
Offset: 0x00000044, Width: 32b; Set the memory size of SDRAM CS3 in unit of kbytes. Range: 0x00000004~0x00400000, i.e. 4~410241024 kilobytes.