NXP chip family identifier.
Revision of silicon. The 'latest' name, means most current revision.
Specify type of memory used by XMCD description.
Specify type of configuration used by XMCD description.
Offset: 0x00000000, Width: 32b; XMCD Header
Offset: 0b, Width: 12b, Configuration block size including XMCD header itself
Offset: 12b, Width: 4b, Configuration block type: 0 - Simplified, 1 - Full
- XMCDCONFIGBLOCKTYPESIMPLIFIED, (0): Simplified configuration block type
- XMCDCONFIGBLOCKTYPEFULL, (1): Full configuration block type
Offset: 16b, Width: 4b, XSPI instance: 0 - XSPI0, 1 - XSPI1
- XMCDXSPI0, (0): XSPI0
- XMCDXSPI1, (1): XSPI1
Offset: 20b, Width: 4b, Memory interface: 0 - XSPI
- XMCDMEMORYINTERFACE_XSPI, (0): XSPI memory interface
Offset: 24b, Width: 4b, Version, fixed value 0x0
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0b, Width: 12b, Configuration block size including XMCD header itself
Offset: 12b, Width: 4b, Configuration block type: 0 - Simplified, 1 - Full
- XMCDCONFIGBLOCKTYPESIMPLIFIED, (0): Simplified configuration block type
- XMCDCONFIGBLOCKTYPEFULL, (1): Full configuration block type
Offset: 16b, Width: 4b, XSPI instance: 0 - XSPI0, 1 - XSPI1
- XMCDXSPI0, (0): XSPI0
- XMCDXSPI1, (1): XSPI1
Offset: 20b, Width: 4b, Memory interface: 0 - XSPI
- XMCDMEMORYINTERFACE_XSPI, (0): XSPI memory interface
Offset: 24b, Width: 4b, Version, fixed value 0x0
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0x00000004, Width: 32b; XMCD Configuration Option 0
Offset: 0b, Width: 8b, Size in MB: 0 - Auto detection, Others - Size in MB
Offset: 8b, Width: 4b, Maximum frequency (SoC specific definitions)
- XMCDXSPIRAMMAXFREQ30MHZ, (1): 30MHz
- XMCDXSPIRAMMAXFREQ50MHZ, (2): 50MHz
- XMCDXSPIRAMMAXFREQ60MHZ, (3): 60MHz
- XMCDXSPIRAMMAXFREQ80MHZ, (4): 80MHz
- XMCDXSPIRAMMAXFREQ100MHZ, (5): 100MHz
- XMCDXSPIRAMMAXFREQ120MHZ, (6): 120MHz
- XMCDXSPIRAMMAXFREQ133MHZ, (7): 133MHz
- XMCDXSPIRAMMAXFREQ166MHZ, (8): 166MHz
- XMCDXSPIRAMMAXFREQ200MHZ, (9): 200MHz
Offset: 12b, Width: 4b, Misc. For HyperRAM: 0 - Differential clock driven, 1 - Single-ended clock driven
- XMCDXSPIRAMMISCDIFFERENTIALCLOCK, (0): Differential clock driven
- XMCDXSPIRAMMISCSINGLEENDED_CLOCK, (1): Single-ended clock driven
Offset: 16b, Width: 4b, Reserved for future use
Offset: 20b, Width: 4b, Device type: 0 - HyperRAM, 1 - APMemory
- XMCDXSPIRAMDEVICETYPEHYPERRAM, (0): HyperRAM
- XMCDXSPIRAMDEVICETYPEAPMEMORY, (1): APMemory
Offset: 24b, Width: 4b, Option Size
- XMCDXSPIOPTIONSIZE1, (0): Option words = 1
- XMCDXSPIOPTIONSIZE2, (1): Option words = 2
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0b, Width: 8b, Size in MB: 0 - Auto detection, Others - Size in MB
Offset: 8b, Width: 4b, Maximum frequency (SoC specific definitions)
- XMCDXSPIRAMMAXFREQ30MHZ, (1): 30MHz
- XMCDXSPIRAMMAXFREQ50MHZ, (2): 50MHz
- XMCDXSPIRAMMAXFREQ60MHZ, (3): 60MHz
- XMCDXSPIRAMMAXFREQ80MHZ, (4): 80MHz
- XMCDXSPIRAMMAXFREQ100MHZ, (5): 100MHz
- XMCDXSPIRAMMAXFREQ120MHZ, (6): 120MHz
- XMCDXSPIRAMMAXFREQ133MHZ, (7): 133MHz
- XMCDXSPIRAMMAXFREQ166MHZ, (8): 166MHz
- XMCDXSPIRAMMAXFREQ200MHZ, (9): 200MHz
Offset: 12b, Width: 4b, Misc. For HyperRAM: 0 - Differential clock driven, 1 - Single-ended clock driven
- XMCDXSPIRAMMISCDIFFERENTIALCLOCK, (0): Differential clock driven
- XMCDXSPIRAMMISCSINGLEENDED_CLOCK, (1): Single-ended clock driven
Offset: 16b, Width: 4b, Reserved for future use
Offset: 20b, Width: 4b, Device type: 0 - HyperRAM, 1 - APMemory
- XMCDXSPIRAMDEVICETYPEHYPERRAM, (0): HyperRAM
- XMCDXSPIRAMDEVICETYPEAPMEMORY, (1): APMemory
Offset: 24b, Width: 4b, Option Size
- XMCDXSPIOPTIONSIZE1, (0): Option words = 1
- XMCDXSPIOPTIONSIZE2, (1): Option words = 2
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0x00000004, Width: 32b; XMCD Configuration Option 0
Offset: 0b, Width: 8b, Size in MB: 0 - Auto detection, Others - Size in MB
Offset: 8b, Width: 4b, Maximum frequency (SoC specific definitions)
- XMCDXSPIRAMMAXFREQ30MHZ, (1): 30MHz
- XMCDXSPIRAMMAXFREQ50MHZ, (2): 50MHz
- XMCDXSPIRAMMAXFREQ60MHZ, (3): 60MHz
- XMCDXSPIRAMMAXFREQ80MHZ, (4): 80MHz
- XMCDXSPIRAMMAXFREQ100MHZ, (5): 100MHz
- XMCDXSPIRAMMAXFREQ120MHZ, (6): 120MHz
- XMCDXSPIRAMMAXFREQ133MHZ, (7): 133MHz
- XMCDXSPIRAMMAXFREQ166MHZ, (8): 166MHz
- XMCDXSPIRAMMAXFREQ200MHZ, (9): 200MHz
Offset: 12b, Width: 4b, Misc. For HyperRAM: 0 - Differential clock driven, 1 - Single-ended clock driven
- XMCDXSPIRAMMISCDIFFERENTIALCLOCK, (0): Differential clock driven
- XMCDXSPIRAMMISCSINGLEENDED_CLOCK, (1): Single-ended clock driven
Offset: 16b, Width: 4b, Reserved for future use
Offset: 20b, Width: 4b, Device type: 0 - HyperRAM, 1 - APMemory
- XMCDXSPIRAMDEVICETYPEHYPERRAM, (0): HyperRAM
- XMCDXSPIRAMDEVICETYPEAPMEMORY, (1): APMemory
Offset: 24b, Width: 4b, Option Size
- XMCDXSPIOPTIONSIZE1, (0): Option words = 1
- XMCDXSPIOPTIONSIZE2, (1): Option words = 2
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0b, Width: 8b, Size in MB: 0 - Auto detection, Others - Size in MB
Offset: 8b, Width: 4b, Maximum frequency (SoC specific definitions)
- XMCDXSPIRAMMAXFREQ30MHZ, (1): 30MHz
- XMCDXSPIRAMMAXFREQ50MHZ, (2): 50MHz
- XMCDXSPIRAMMAXFREQ60MHZ, (3): 60MHz
- XMCDXSPIRAMMAXFREQ80MHZ, (4): 80MHz
- XMCDXSPIRAMMAXFREQ100MHZ, (5): 100MHz
- XMCDXSPIRAMMAXFREQ120MHZ, (6): 120MHz
- XMCDXSPIRAMMAXFREQ133MHZ, (7): 133MHz
- XMCDXSPIRAMMAXFREQ166MHZ, (8): 166MHz
- XMCDXSPIRAMMAXFREQ200MHZ, (9): 200MHz
Offset: 12b, Width: 4b, Misc. For HyperRAM: 0 - Differential clock driven, 1 - Single-ended clock driven
- XMCDXSPIRAMMISCDIFFERENTIALCLOCK, (0): Differential clock driven
- XMCDXSPIRAMMISCSINGLEENDED_CLOCK, (1): Single-ended clock driven
Offset: 16b, Width: 4b, Reserved for future use
Offset: 20b, Width: 4b, Device type: 0 - HyperRAM, 1 - APMemory
- XMCDXSPIRAMDEVICETYPEHYPERRAM, (0): HyperRAM
- XMCDXSPIRAMDEVICETYPEAPMEMORY, (1): APMemory
Offset: 24b, Width: 4b, Option Size
- XMCDXSPIOPTIONSIZE1, (0): Option words = 1
- XMCDXSPIOPTIONSIZE2, (1): Option words = 2
Offset: 28b, Width: 4b, Tag, fixed value 0xC
Offset: 0x00000008, Width: 32b; XMCD Configuration Option 1
Offset: 0b, Width: 4b, Read dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 4b, Width: 4b, Write dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 8b, Width: 7b, Maximum CS Low time - value x 0.1 μs
Offset: 15b, Width: 1b, Bus width
- XMCDXSPIBUSWIDTHX8, (0): X8 mode
- XMCDXSPIBUSWIDTHX16, (1): X16 mode
Offset: 24b, Width: 4b, Reserved for future use
Offset: 28b, Width: 4b, RAM connection: 0 - PORTA
- XMCDXSPIRAMCONNECTIONPORTA, (0): PORTA
Offset: 0b, Width: 4b, Read dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 4b, Width: 4b, Write dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 8b, Width: 7b, Maximum CS Low time - value x 0.1 μs
Offset: 15b, Width: 1b, Bus width
- XMCDXSPIBUSWIDTHX8, (0): X8 mode
- XMCDXSPIBUSWIDTHX16, (1): X16 mode
Offset: 24b, Width: 4b, Reserved for future use
Offset: 28b, Width: 4b, RAM connection: 0 - PORTA
- XMCDXSPIRAMCONNECTIONPORTA, (0): PORTA
Offset: 0x00000008, Width: 32b; XMCD Configuration Option 1
Offset: 0b, Width: 4b, Read dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 4b, Width: 4b, Write dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 8b, Width: 7b, Maximum CS Low time - value x 0.1 μs
Offset: 15b, Width: 1b, Bus width
- XMCDXSPIBUSWIDTHX8, (0): X8 mode
- XMCDXSPIBUSWIDTHX16, (1): X16 mode
Offset: 24b, Width: 4b, Reserved for future use
Offset: 28b, Width: 4b, RAM connection: 0 - PORTA
- XMCDXSPIRAMCONNECTIONPORTA, (0): PORTA
Offset: 0b, Width: 4b, Read dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 4b, Width: 4b, Write dummy cycles: 0 - Auto detection, Others - Specified dummy cycles
Offset: 8b, Width: 7b, Maximum CS Low time - value x 0.1 μs
Offset: 15b, Width: 1b, Bus width
- XMCDXSPIBUSWIDTHX8, (0): X8 mode
- XMCDXSPIBUSWIDTHX16, (1): X16 mode
Offset: 24b, Width: 4b, Reserved for future use
Offset: 28b, Width: 4b, RAM connection: 0 - PORTA
- XMCDXSPIRAMCONNECTIONPORTA, (0): PORTA