i.MX 95 signed AHAB with U-BOOT

This notebook describes how to build a bootable signed AHAB image with ELE firmware and U-BOOT bootloader.

1. Prerequisites

• SPSDK is needed with examples extension. pip install spsdk[examples] (Please refer to the installation documentation.)

• This demo was tested with i.MX 95 EVK board with LPDDR5 memory and A1 chip revision.

1.1 Images preparation

• To create resulting binary containing AHAB containers, we need to prepare the binaries

• In this section we reproduce the process which is done by the imx-mkimage tool

• Obtain all the necessary binaries and put them into inputs directory

1.2 U-Boot

In order to use the nxpele app, U-Boot must be built with AHAB support. CONFIG_AHAB_BOOT=y If you want to use the nxpele over fastboot, also multiplexing of console output to fastboot must be enabled by setting CONFIG_CONSOLE_MUX=y.

1.3 Requirements

Download these files from the https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/<package name> and put them into the inputs directory.

Primary image container set:

• ELE firmware

• LPDDR5 or LPDDR5 firmware files with OEI firmware

• CM33 OEI TCM

• CM33 System manager image

• U-Boot SPL

• [Optional] M7 application image

• Four ECC keys (In this example we use ECC384). Might be created with nxpcrypto tool.

Secondary image container set

• bl31.bin binary (ARM Trusted Firmware)

• U-Boot (built with AHAB support)

• TEE binary

• Four ECC keys (Same as in the primary container).

2. AHAB Image

2.1 AHAB Template

We can generate the template using the nxpimage ahab get-template command. The command will generate a template. The template is a YAML file that contains the AHAB header and the AHAB container. The AHAB header contains the information about the image, such as the version, the number of containers, and the signature. The AHAB container contains the information about the image, such as the image type, the image version, the image size, and the image signature.

The following command generates the template:

nxpimage ahab get-template -f mimx9596 -o ahab_template.yaml

2.2 Exporting of the AHAB image

The AHAB image can be exported using the nxpimage ahab export command. The command will create the AHAB image from the template. The following command creates the AHAB image:

nxpimage ahab export -c ahab_template.yaml 

2.4 Primary image container set

Primary image container set consists of the following images:

• ELE firmware

• DDR firmware with OEI

• System manager

• U-Boot SPL

• [Optional] M7 application image

nxpimage ahab get-template -r a1 -f mimx9596 -o workspace/ahab_template.yaml --force 
Creating workspace/ahab_template.yaml template file.

Configuration Differences

Show Diff Download Config

# ========================  Advanced High-Assurance Boot Configuration template for mimx9596.  =========================

# ======================================================================================================================
#                                                 == General Options ==                                                 
# ======================================================================================================================
# -------------------------------------===== The chip family name [Required] =====--------------------------------------
# Description: NXP chip family identifier.
# Possible options: 
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon. The 'latest' name, means most current revision.
# Possible options: 
revision: a1 IMPORTANT! Change the revision to A1/A0, latest B0 revision has different container format
# -----------------------------------------===== Target memory [Optional] =====-----------------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: generated_ahab.bin
output: ../outputs/primary_signed_ahab.bin
container_version: 1
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  -
  # ====================================================================================================================
  #                                          == List of possible 2 options. ==                                          
  #                                        Options [binary_container, container]                                        
  # ====================================================================================================================

  #  =========================== [Example of possible configuration: #0 , erase if not used] ============================
    # -----------------------------------===== Binary AHAB container [Required] =====-----------------------------------
    # Description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware.
    binary_container: Define the path to the EdgeLock Enclave Firmware container
      # -----------------------------===== The AHAB container binary file [Required] =====------------------------------
      # Description: The binary file that contains AHAB "my_binary_container.bin
      path: my_ahab_container.bin
      path: ./mx95a0-ahab-container.img

  #  =========================== [Example of possible configuration: #1 , erase if not used] ============================
    # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: none Define set is used to authenticate the container
      srk_set: oem
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      check_all_signatures: default
      fast_boot: enabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # -------------------------------===== AHAB container signing key [Optional] =====--------------------------------
      # Description: Private key used for sign the container header. Header can be signed by SRK. The referenced SRK
      # must not have been revoked.
      signing_key: ../../../_data/keys/ecc384/srk0_ecc384.pem
      signing_key: my_signing_key.pem Define the path to the private key.
      # -----------------------------------===== Signature Provider [Optional] =====------------------------------------
      # Description: Signature provider configuration in format 'type=;=;='. The
      # signature provider could be used instead of definition of 'signing_key'.
      signature_provider: type=file;file_path=my_prv_key.pem

      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==                     
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        -
        # ==============================================================================================================
        #                                       == List of possible 11 options. ==                                      
        #      Options [Double Authentication of NXP Firmwares, OEI with DDR tunning images, OEI TCM Settings (ECC      
        # configuration etc.), Boot system manager, Cortex M7 additional application, SPL, V2X Dummy, Uboot ATF, Uboot, 
        #                            TEE Trusted Execution Environment, General Image Entry]                            
        # ==============================================================================================================

        #  ===== [Example of possible configuration: #0 Double Authentication of NXP Firmwares, erase if not used] ======
        # Double Authentication of NXP firmwares
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000000000000
        # hash_type:                     SHA384
          # -------------------------------------===== NXP ELE FW [Required] =====--------------------------------------
          # Description: NXP ELE firmware, that should be also signed by OEM keys binary file.
          double_authentication: nxp_ele.bin

        #  =========== [Example of possible configuration: #1 OEI with DDR tunning images, erase if not used] ===========
        # OEI with DDR PHY tunning images
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -----------------------------------===== LPDDR memory FW [Required] =====-----------------------------------
          # Description: Firmware for LPDDR4/5 memory.
          lpddr_imem: lpddr_imem.bin Add path to the LPDDR IMEM image
          lpddr_imem: ./lpddr5_imem_v202311.bin
          # ---------------------------===== LPDDR memory FW for quick boot [Optional] =====----------------------------
          # Description: Firmware for LPDDR4/5 for quick boot.
          lpddr_imem_qb: lpddr_imem_qb.bin Add path to the LPDDR IMEM image
          lpddr_imem_qb: ./lpddr5_imem_qb_v202311.bin
          # ----------------------------------===== LPDDR memory data [Required] =====----------------------------------
          # Description: Data for LPDDR4/5 memory.
          lpddr_dmem: lpddr_dmem.bin Add path to the LPDDR DMEM image
          lpddr_dmem: ./lpddr5_dmem_v202311.bin
          # --------------------------===== LPDDR memory data for quick boot [Optional] =====---------------------------
          # Description: Data for LPDDR4/5 memory in quick boot.
          lpddr_dmem_qb: lpddr_dmem_qb.bin Optionally add path to the LPDDR DMEM quick boot image
          lpddr_dmem_qb: ./lpddr5_dmem_qb_v202311.bin
          # -----------------------------------------===== OEI [Required] =====-----------------------------------------
          # Description: OEI - Optional Executable Image firmware
          oei_ddr: oei_ddr.bin Add path to the OEI DDR image
          oei_ddr: ./oei-m33-ddr.bin
          # -----------------------------------===== Quick Boot Data [Optional] =====-----------------------------------
          # Description: QB data - Optional Quick boot data, if defined a new empty record will be added just behing DDR
          # FW entry
          qb_data: qb_data.bin

        #  ==== [Example of possible configuration: #2 OEI TCM Settings (ECC configuration etc.), erase if not used] ====
        # OEI TCM settings (ECC etc.)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -------------------------------------===== OEI TCM FW [Required] =====--------------------------------------
          # Description: OEI(Optional Executable Image) TCM settings binary file.
          oei_tcm: oei_tcm.bin Add path to the OEI TCM image
        - oei_tcm: ./oei-m33-tcm.bin

        #  =============== [Example of possible configuration: #3 Boot system manager, erase if not used] ===============
        # System booting image
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # image_type:                    executable
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # ---------------------------------===== Boot system manager [Required] =====---------------------------------
          # Description: System manager booting image
          system_manager: system_manager.bin Add path to system manager
        - system_manager: ./m33_image-mx95evk.bin

        #  ======== [Example of possible configuration: #4 Cortex M7 additional application, erase if not used] =========
        # Cortex M7 additional application
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x00000000303C0000
        # entry_point:                   0x0000000000000000
        # image_type:                    executable
        # core_id:                       cortex-m7-1
        # meta_data_start_cpu_id:        1
        # hash_type:                     SHA384
          # --------------------------===== Cortex M7 additional application [Required] =====---------------------------
          # Description: Cortex M7 additional application
          cortex_m7_app: cortex_m7_app.bin Optionally Add path to the Cortex M7 application
        - cortex_m7_app: ./hello_world_sm_cm7.bin

        #  ======================= [Example of possible configuration: #5 SPL, erase if not used] =======================
        # U-Boot SPL (Secondary program loader)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000020480000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== SPL [Required] =====-----------------------------------------
          # Description: SPL firmware
          spl: spl.bin Add path to the U-Boot SPL image
        - spl: ./u-boot-spl_mx95_19x19.bin

        #  ==================== [Example of possible configuration: #6 V2X Dummy, erase if not used] ====================
        # V2X dummy image container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008B000000
        # image_type:                    v2x_dummy
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # --------------------------------------===== V2X Dummy [Required] =====--------------------------------------
          # Description: If Present, V2X dummy image will be added to Image Array Entry (no data record)
          v2x_dummy: true This is a dummy image that has to be present in the container for A0
        - v2x_dummy: true

        #  ==================== [Example of possible configuration: #7 Uboot ATF, erase if not used] ====================
        # U-Boot ATF container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008A200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -------------------------------------===== ATF binary [Required] =====--------------------------------------
          # Description: ARM Trusted Firmware binary file.
          atf: bl31.bin

        #  ====================== [Example of possible configuration: #8 Uboot, erase if not used] ======================
        # U-Boot container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000090200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # ------------------------------------===== U-Boot binary [Required] =====------------------------------------
          # Description: U-Boot binary file.
          uboot: u-boot.bin

        #  ======== [Example of possible configuration: #9 TEE Trusted Execution Environment, erase if not used] ========
        # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008C000000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== TEE [Required] =====-----------------------------------------
          # Description: TEE - Trusted Execution Environment binary
          tee: tee.bin

        #  ============== [Example of possible configuration: #10 General Image Entry, erase if not used] ===============
        # General Image Entry
          # -------------------------------------===== Image path [Optional] =====--------------------------------------
          # Description: Path to image binary (absolute/relative). In case that only Image Array entry without any data
          # image is needed, Just do not use the image path. In case that the image size in container should be aligned
          # differently then SPSDK do (4 bytes for ELE images, 1 byte otherwise), there is hidden option
          # 'image_size_alignment' where could be override image size by any custom value.
          image_path: my_image.bin
          # ---------------------------===== Image offset in AHAB container [Optional] =====----------------------------
          # Description: Offset in bytes from start of container header to beginning of the image. Zero value means
          # automatic placing the image with proper alignment after previous one, this is recommended for
          # serial_downloader mode. In case of XiP type of AHAB image, the load_address and entry_point must correspond
          # to this values. Example of setting of load_address - AHAB_IMAGE_ADDRESS+IMAGE_OFFSET=LOAD_ADDRESS. The
          # Booting core images must be located after the other ones
          image_offset: 0
          # ------------------------------===== Image destination address [Required] =====------------------------------
          # Description: Address the image is written to in memory (absolute address in system memory).
          load_address: '0x1FFC_0000'
          # ----------------------------------===== Image entry point [Required] =====----------------------------------
          # Description: Image entry point (absolute address). Valid only for executable image types.
          entry_point: '0x1FFC_0000'
          # -------------------------------------===== Image type [Required] =====--------------------------------------
          # Description: Kind of image.
          # Possible options: 
          # executable_fast_boot_image, v2x_dummy, ele_as_image, ele, v2x_as_image, v2x_primary, v2x_secondary,
          # v2x_rom_patch>
          image_type: executable
          # ---------------------------------------===== Core ID [Required] =====---------------------------------------
          # Description: Defines the core the image is dedicated for. Not all cores are supported for all families.
          # Possible options: 
          core_id: cortex-m33
          # ----------------------------------===== Image encryption [Required] =====-----------------------------------
          # Description: Determines, whether image is encrypted or not.
          is_encrypted: false
          # -------------------------------------===== Boot flags [Optional] =====--------------------------------------
          # Description: Boot flags controlling SCFW boot.
          boot_flags: 0
          # ------------------------------------===== Start CPU ID [Optional] =====-------------------------------------
          # Description: Resource ID of CPU to be started
          meta_data_start_cpu_id: 0
          # ------------------------------===== CPU memory unit start ID [Optional] =====-------------------------------
          # Description: Resource ID of the MU associated with the CPU
          meta_data_mu_cpu_id: 0
          # ---------------------------------===== Start partition ID [Optional] =====----------------------------------
          # Description: Partition ID of the partition to start
          meta_data_start_partition_id: 0
          # ----------------------------------===== Images HASH type [Optional] =====-----------------------------------
          # Description: HASH type of image.
          # Possible options: 
          hash_type: sha512

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==                                      
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys
        flag_ca: false
        flag_ca: true
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - my_srk_public_key0.pub
          - my_srk_public_key1.pub
          - my_srk_public_key2.pub
          - my_srk_public_key3.pub
          - ../../../_data/keys/ecc384/srk0_ecc384.pub
          - ../../../_data/keys/ecc384/srk1_ecc384.pub
          - ../../../_data/keys/ecc384/srk2_ecc384.pub
          - ../../../_data/keys/ecc384/srk3_ecc384.pub

      # ================================================================================================================
      #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
      # ================================================================================================================
      # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
      # Description: Encryption blob container definition
      blob:
        # ------------------------------------===== Key identifier [Required] =====-------------------------------------
        # Description: The key identifier that has been used to generate DEK keyblob.
        key_identifier: 0
        # -------------------------------------===== DEK key size [Required] =====--------------------------------------
        # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
        # Possible options: <128, 192, 256>
        dek_key_size: 128
        # ----------------------------------------===== DEK key [Required] =====----------------------------------------
        # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
        dek_key: my_dek_key.txt
        # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
        # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
        # If NOT used, the empty keyblob is inserted into container and need to be updated later.
        dek_keyblob: my_wrapped_key.txt All attributes related to the encrypting

# Copyright 2024 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
# ==========================  Advanced High-Assurance Boot Configuration template for mimx9596.  ===========================

# ======================================================================================================================
#                                                 == General Options ==
# ======================================================================================================================
# ------------------------------------------===== MCU family [Required] =====-------------------------------------------
# Description: Family identifier including the chip revision. If revision is not present, latest revision is used as
# default.
# Possible options: 
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon
revision: a1 IMPORTANT! Change the revision to A1/A0, latest B0 revision has different container format
# ----------------------------------===== Target memory [Conditionally required] =====----------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: ../outputs/primary_signed_ahab.bin
# ---------------------------------------===== Container version [Optional] =====---------------------------------------
# Description: Force container version, if not specified the default version is used. This configuration option is valid
# only for chips that supports both AHAB container versions. Possible options <2, 1>
container_version: 1
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  -
    # -----------------------------------===== Binary AHAB container [Required] =====-----------------------------------
    # Description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware.
    binary_container: Define the path to the EdgeLock Enclave Firmware container
      # -----------------------------===== The AHAB container binary file [Required] =====------------------------------
      # Description: The binary file that contains AHAB "my_binary_container.bin
      path: ./mx95a0-ahab-container.img

  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: oem Define set is used to authenticate the container
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      # ----------------------------------===== Check all signatures [Optional] =====-----------------------------------
      # Description: This option overrides a fuse to select verification mode.
      #  - default: Apply default fuse policy.
      #  - check_all_signatures: Force verification of all present signatures.
      # Possible options: 
      check_all_signatures: default
      # ----------------------------------------===== Fast boot [Optional] =====----------------------------------------
      # Description: This option enables fast boot mode.
      #  - enabled: Fast boot enabled.
      #  - slice_hash: Slice and hash mode.
      #  - on_fly: On the fly hash.
      # Possible options: 
      fast_boot: enabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # -------------------------------===== AHAB container signing key [Optional] =====--------------------------------
      # Description: Private key used for sign the container header. Header can be signed by SRK. The referenced SRK
      # must not have been revoked.
      signing_key: ../../../_data/keys/ecc384/srk0_ecc384.pem Define the path to the private key.

      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        -
          # OEI with DDR PHY tunning images
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00010400
          # load_address:                  0x000000001FFC0000
          # entry_point:                   0x000000001FFC0001
          # image_type:                    executable
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # -----------------------------===== LPDDR memory FW in 1D mode [Required] =====------------------------------
          # Description: Firmware for LPDDR4/5 memory in 1D mode.
          lpddr_imem: ./lpddr5_imem_v202311.bin Add path to the LPDDR IMEM image
          # -----------------------------===== LPDDR memory FW in 2D mode [Required] =====------------------------------
          # Description: Firmware for LPDDR4/5 memory in 2D mode.
          lpddr_imem_qb: ./lpddr5_imem_qb_v202311.bin Add path to the LPDDR IMEM image
          # ----------------------------===== LPDDR memory data in 1D mode [Required] =====-----------------------------
          # Description: Data for LPDDR4/5 memory in 1D mode.
          lpddr_dmem: ./lpddr5_dmem_v202311.bin Add path to the LPDDR DMEM image
          # ----------------------------===== LPDDR memory data in 2D mode [Required] =====-----------------------------
          # Description: Data for LPDDR4/5 memory in 2D mode.
          lpddr_dmem_qb: ./lpddr5_dmem_qb_v202311.bin Optionally add path to the LPDDR DMEM quick boot image
          # -----------------------------------------===== OEI [Required] =====-----------------------------------------
          # Description: OEI - Optional Executable Image firmware
          oei_ddr: ./oei-m33-ddr.bin Add path to the OEI DDR image

          # OEI TCM settings (ECC etc.)
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00010400
          # load_address:                  0x000000001FFC0000
          # entry_point:                   0x000000001FFC0001
          # image_type:                    executable
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # -------------------------------------===== OEI TCM FW [Required] =====--------------------------------------
          # Description: OEI(Optional Executable Image) TCM settings binary file.
        - oei_tcm: ./oei-m33-tcm.bin Add path to the OEI TCM image

          # System booting image
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00080400
          # load_address:                  0x000000001FFC0000
          # image_type:                    executable
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # ---------------------------------===== Boot system manager [Required] =====---------------------------------
          # Description: System manager booting image
        - system_manager: ./m33_image-mx95evk.bin Add path to system manager

          # Cortex M7 additional application
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x00000000303C0000
          # image_type:                    executable
          # core_id:                       cortex-m7-1
          # hash_type:                     SHA384
          # --------------------------===== Cortex M7 additional application [Required] =====---------------------------
          # Description: Cortex M7 additional application
        - cortex_m7_app: ./hello_world_sm_cm7.bin Optionally Add path to the Cortex M7 application

          # U-Boot SPL (Secondary program loader)
          # Image array default settings. Can be override by defines that are hidden in template:
          # image_offset:                  0x00010400
          # load_address:                  0x0000000020480000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # hash_type:                     SHA384
          # -----------------------------------------===== SPL [Required] =====-----------------------------------------
          # Description: SPL firmware
        - spl: ./u-boot-spl_mx95_19x19.bin Add path to the U-Boot SPL image

          # V2X dummy image container definition
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x000000008B000000
          # image_type:                    v2x_dummy
          # core_id:                       cortex-m33
          # hash_type:                     SHA384
          # --------------------------------------===== V2X Dummy [Required] =====--------------------------------------
          # Description: If Present, V2X dummy image will be added to Image Array Entry (no data record)
        - v2x_dummy: true This is a dummy image that has to be present in the container for A0

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==                                      
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys
        flag_ca: true
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - ../../../_data/keys/ecc384/srk0_ecc384.pub
          - ../../../_data/keys/ecc384/srk1_ecc384.pub
          - ../../../_data/keys/ecc384/srk2_ecc384.pub
          - ../../../_data/keys/ecc384/srk3_ecc384.pub

2.5 Secondary image container set

Secondary image container set consists of the following images:

• bl31.bin binary (ARM Trusted Firmware)

• U-Boot (built with AHAB support)

• TEE binary

YamlDiffWidget("inputs/mx95_signed_ahab_secondary.diffc").html

nxpimage ahab get-template -r a1 -f mimx9596 -o workspace/ahab_template.yaml --force 
Creating workspace/ahab_template.yaml template file.

Configuration Differences

Show Diff Download Config

# ========================  Advanced High-Assurance Boot Configuration template for mimx9596.  =========================

# ======================================================================================================================
#                                                 == General Options ==                                                 
# ======================================================================================================================
# -------------------------------------===== The chip family name [Required] =====--------------------------------------
# Description: NXP chip family identifier.
# Possible options: 
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon. The 'latest' name, means most current revision.
# Possible options: 
revision: a1 IMPORTANT! Change the revision to A0/A1, latest B0 revision has different container format
# -----------------------------------------===== Target memory [Optional] =====-----------------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: generated_ahab.bin
output: ../outputs/secondary_signed_ahab.bin
container_version: 1
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  -
  # ====================================================================================================================
  #                                          == List of possible 2 options. ==                                          
  #                                        Options [binary_container, container]                                        
  # ====================================================================================================================

  #  =========================== [Example of possible configuration: #0 , erase if not used] ============================
    # -----------------------------------===== Binary AHAB container [Required] =====-----------------------------------
    # Description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware.
    binary_container:
      # -----------------------------===== The AHAB container binary file [Required] =====------------------------------
      # Description: The binary file that contains AHAB "my_binary_container.bin
      path: my_ahab_container.bin

  #  =========================== [Example of possible configuration: #1 , erase if not used] ============================
    # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: none Define set is used to authenticate the container
      srk_set: oem
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      check_all_signatures: default
      fast_boot: enabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # -------------------------------===== AHAB container signing key [Optional] =====--------------------------------
      # Description: Private key used for sign the container header. Header can be signed by SRK. The referenced SRK
      # must not have been revoked.
      signing_key: ../_data/keys/ecc384/srk0_ecc384.pem
      signing_key: my_signing_key.pem
      # -----------------------------------===== Signature Provider [Optional] =====------------------------------------
      # Description: Signature provider configuration in format 'type=;=;='. The
      # signature provider could be used instead of definition of 'signing_key'.
      signature_provider: type=file;file_path=my_prv_key.pem

      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==                     
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        -
        # ==============================================================================================================
        #                                       == List of possible 11 options. ==                                      
        #      Options [Double Authentication of NXP Firmwares, OEI with DDR tunning images, OEI TCM Settings (ECC      
        # configuration etc.), Boot system manager, Cortex M7 additional application, SPL, V2X Dummy, Uboot ATF, Uboot, 
        #                            TEE Trusted Execution Environment, General Image Entry]                            
        # ==============================================================================================================

        #  ===== [Example of possible configuration: #0 Double Authentication of NXP Firmwares, erase if not used] ======
        # Double Authentication of NXP firmwares
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000000000000
        # hash_type:                     SHA384
          # -------------------------------------===== NXP ELE FW [Required] =====--------------------------------------
          # Description: NXP ELE firmware, that should be also signed by OEM keys binary file.
          double_authentication: nxp_ele.bin

        #  =========== [Example of possible configuration: #1 OEI with DDR tunning images, erase if not used] ===========
        # OEI with DDR PHY tunning images
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -----------------------------------===== LPDDR memory FW [Required] =====-----------------------------------
          # Description: Firmware for LPDDR4/5 memory.
          lpddr_imem: lpddr_imem.bin
          # ---------------------------===== LPDDR memory FW for quick boot [Optional] =====----------------------------
          # Description: Firmware for LPDDR4/5 for quick boot.
          lpddr_imem_qb: lpddr_imem_qb.bin
          # ----------------------------------===== LPDDR memory data [Required] =====----------------------------------
          # Description: Data for LPDDR4/5 memory.
          lpddr_dmem: lpddr_dmem.bin
          # --------------------------===== LPDDR memory data for quick boot [Optional] =====---------------------------
          # Description: Data for LPDDR4/5 memory in quick boot.
          lpddr_dmem_qb: lpddr_dmem_qb.bin
          # -----------------------------------------===== OEI [Required] =====-----------------------------------------
          # Description: OEI - Optional Executable Image firmware
          oei_ddr: oei_ddr.bin
          # -----------------------------------===== Quick Boot Data [Optional] =====-----------------------------------
          # Description: QB data - Optional Quick boot data, if defined a new empty record will be added just behing DDR
          # FW entry
          qb_data: qb_data.bin

        #  ==== [Example of possible configuration: #2 OEI TCM Settings (ECC configuration etc.), erase if not used] ====
        # OEI TCM settings (ECC etc.)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # entry_point:                   0x000000001FFC0001
        # image_type:                    oei
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # -------------------------------------===== OEI TCM FW [Required] =====--------------------------------------
          # Description: OEI(Optional Executable Image) TCM settings binary file.
          oei_tcm: oei_tcm.bin

        #  =============== [Example of possible configuration: #3 Boot system manager, erase if not used] ===============
        # System booting image
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000001FFC0000
        # image_type:                    executable
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # ---------------------------------===== Boot system manager [Required] =====---------------------------------
          # Description: System manager booting image
          system_manager: system_manager.bin

        #  ======== [Example of possible configuration: #4 Cortex M7 additional application, erase if not used] =========
        # Cortex M7 additional application
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x00000000303C0000
        # entry_point:                   0x0000000000000000
        # image_type:                    executable
        # core_id:                       cortex-m7-1
        # meta_data_start_cpu_id:        1
        # hash_type:                     SHA384
          # --------------------------===== Cortex M7 additional application [Required] =====---------------------------
          # Description: Cortex M7 additional application
          cortex_m7_app: cortex_m7_app.bin

        #  ======================= [Example of possible configuration: #5 SPL, erase if not used] =======================
        # U-Boot SPL (Secondary program loader)
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000020480000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== SPL [Required] =====-----------------------------------------
          # Description: SPL firmware
          spl: spl.bin

        #  ==================== [Example of possible configuration: #6 V2X Dummy, erase if not used] ====================
        # V2X dummy image container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008B000000
        # image_type:                    v2x_dummy
        # core_id:                       cortex-m33
        # hash_type:                     SHA384
          # --------------------------------------===== V2X Dummy [Required] =====--------------------------------------
          # Description: If Present, V2X dummy image will be added to Image Array Entry (no data record)
          v2x_dummy: true

        #  ==================== [Example of possible configuration: #7 Uboot ATF, erase if not used] ====================
        # U-Boot ATF container definition
        - # U-Boot ATF container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008A200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -------------------------------------===== ATF binary [Required] =====--------------------------------------
          # Description: ARM Trusted Firmware binary file.
          atf: bl31.bin Define path to the ARM Trusted Firmware
          atf: ./bl31-imx95.bin-optee

        #  ====================== [Example of possible configuration: #8 Uboot, erase if not used] ======================
        # U-Boot container definition
        - # U-Boot container definition
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x0000000090200000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # ------------------------------------===== U-Boot binary [Required] =====------------------------------------
          # Description: U-Boot binary file.
          uboot: u-boot.bin Define path to the U-Boot binary file
          uboot: ./u-boot.bin

        #  ======== [Example of possible configuration: #9 TEE Trusted Execution Environment, erase if not used] ========
        # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
        - # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
        # Image array default settings. Can be overridden by definitions that are hidden in the template:
        # load_address:                  0x000000008C000000
        # image_type:                    executable
        # core_id:                       cortex-a55
        # meta_data_start_cpu_id:        2
        # hash_type:                     SHA384
          # -----------------------------------------===== TEE [Required] =====-----------------------------------------
          # Description: TEE - Trusted Execution Environment binary
          tee: tee.bin Define path to the TEE (Trusted Execution Environment)
          tee: ./tee.bin

        #  ============== [Example of possible configuration: #10 General Image Entry, erase if not used] ===============
        # General Image Entry
          # -------------------------------------===== Image path [Optional] =====--------------------------------------
          # Description: Path to image binary (absolute/relative). In case that only Image Array entry without any data
          # image is needed, Just do not use the image path. In case that the image size in container should be aligned
          # differently then SPSDK do (4 bytes for ELE images, 1 byte otherwise), there is hidden option
          # 'image_size_alignment' where could be override image size by any custom value.
          image_path: my_image.bin
          # ---------------------------===== Image offset in AHAB container [Optional] =====----------------------------
          # Description: Offset in bytes from start of container header to beginning of the image. Zero value means
          # automatic placing the image with proper alignment after previous one, this is recommended for
          # serial_downloader mode. In case of XiP type of AHAB image, the load_address and entry_point must correspond
          # to this values. Example of setting of load_address - AHAB_IMAGE_ADDRESS+IMAGE_OFFSET=LOAD_ADDRESS. The
          # Booting core images must be located after the other ones
          image_offset: 0
          # ------------------------------===== Image destination address [Required] =====------------------------------
          # Description: Address the image is written to in memory (absolute address in system memory).
          load_address: '0x1FFC_0000'
          # ----------------------------------===== Image entry point [Required] =====----------------------------------
          # Description: Image entry point (absolute address). Valid only for executable image types.
          entry_point: '0x1FFC_0000'
          # -------------------------------------===== Image type [Required] =====--------------------------------------
          # Description: Kind of image.
          # Possible options: 
          # executable_fast_boot_image, v2x_dummy, ele_as_image, ele, v2x_as_image, v2x_primary, v2x_secondary,
          # v2x_rom_patch>
          image_type: executable
          # ---------------------------------------===== Core ID [Required] =====---------------------------------------
          # Description: Defines the core the image is dedicated for. Not all cores are supported for all families.
          # Possible options: 
          core_id: cortex-m33
          # ----------------------------------===== Image encryption [Required] =====-----------------------------------
          # Description: Determines, whether image is encrypted or not.
          is_encrypted: false
          # -------------------------------------===== Boot flags [Optional] =====--------------------------------------
          # Description: Boot flags controlling SCFW boot.
          boot_flags: 0
          # ------------------------------------===== Start CPU ID [Optional] =====-------------------------------------
          # Description: Resource ID of CPU to be started
          meta_data_start_cpu_id: 0
          # ------------------------------===== CPU memory unit start ID [Optional] =====-------------------------------
          # Description: Resource ID of the MU associated with the CPU
          meta_data_mu_cpu_id: 0
          # ---------------------------------===== Start partition ID [Optional] =====----------------------------------
          # Description: Partition ID of the partition to start
          meta_data_start_partition_id: 0
          # ----------------------------------===== Images HASH type [Optional] =====-----------------------------------
          # Description: HASH type of image.
          # Possible options: 
          hash_type: sha512

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==                                      
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys
        flag_ca: false
        flag_ca: true
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - my_srk_public_key0.pub
          - my_srk_public_key1.pub
          - my_srk_public_key2.pub
          - my_srk_public_key3.pub
          - ../_data/keys/ecc384/srk0_ecc384.pub
          - ../_data/keys/ecc384/srk1_ecc384.pub
          - ../_data/keys/ecc384/srk2_ecc384.pub
          - ../_data/keys/ecc384/srk3_ecc384.pub

      # ================================================================================================================
      #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
      # ================================================================================================================
      # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
      # Description: Encryption blob container definition
      blob:
        # ------------------------------------===== Key identifier [Required] =====-------------------------------------
        # Description: The key identifier that has been used to generate DEK keyblob.
        key_identifier: 0
        # -------------------------------------===== DEK key size [Required] =====--------------------------------------
        # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
        # Possible options: <128, 192, 256>
        dek_key_size: 128
        # ----------------------------------------===== DEK key [Required] =====----------------------------------------
        # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
        dek_key: my_dek_key.txt
        # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
        # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
        # If NOT used, the empty keyblob is inserted into container and need to be updated later.
        dek_keyblob: my_wrapped_key.txt All attributes related to the encrypting

# Copyright 2024 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
# ==========================  Advanced High-Assurance Boot Configuration template for mimx9596.  ===========================

# ======================================================================================================================
#                                                 == General Options ==
# ======================================================================================================================
# ------------------------------------------===== MCU family [Required] =====-------------------------------------------
# Description: Family identifier including the chip revision. If revision is not present, latest revision is used as
# default.
# Possible options: 
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon
revision: a1 IMPORTANT! Change the revision to A0/A1, latest B0 revision has different container format
# ----------------------------------===== Target memory [Conditionally required] =====----------------------------------
# Description: Target memory for AHAB container
# Possible options: 
target_memory: standard
# ---------------------------------------===== Output file name [Required] =====----------------------------------------
# Description: Output AHAB file name
output: ../outputs/secondary_signed_ahab.bin
# ---------------------------------------===== Container version [Optional] =====---------------------------------------
# Description: Force container version, if not specified the default version is used. This configuration option is valid
# only for chips that supports both AHAB container versions. Possible options <2, 1>
container_version: 1
# ------------------------------===== List of containers present in AHAB [Required] =====-------------------------------
# Description: The order of containers in the list defines the order in AHAB.
containers:
  - # --------------------------------------===== AHAB Container [Required] =====---------------------------------------
    # Description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB
    # container.
    container:
      # --------------------------------===== Super Root Key (SRK) set [Required] =====---------------------------------
      # Description: Defines which set is used to authenticate the container.
      # Possible options: 
      srk_set: oem Define set is used to authenticate the container
      # ---------------------------------===== Used SRK [Conditionally required] =====----------------------------------
      # Description: Which key from SRK set is being used.
      used_srk_id: 0
      # -------------------------------------===== SRK revoke mask [Optional] =====-------------------------------------
      # Description: Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke key. Bit 0 = revoke SRK_0, bit
      # 1 = revoke SRK_1 etc. Example of revocation SRK_0 and SRK_1 - the value should be 0x03
      srk_revoke_mask: '0x00'
      # ----------------------------------===== GDET runtime behavior [Optional] =====----------------------------------
      # Description: This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE
      # firmware.
      #  - disabled:       GDET is disabled after the first OEM container has been authenticated (default behavior)
      #  - enabled_eleapi: Automatically enable GDET during all ELE API calls
      #  - enabled:        Leave GDET enabled
      # Possible options: 
      gdet_runtime_behavior: disabled
      # ----------------------------------===== Check all signatures [Optional] =====-----------------------------------
      # Description: This option overrides a fuse to select verification mode.
      #  - default: Apply default fuse policy.
      #  - check_all_signatures: Force verification of all present signatures.
      # Possible options: 
      check_all_signatures: default
      # ----------------------------------------===== Fast boot [Optional] =====----------------------------------------
      # Description: This option enables fast boot mode.
      #  - enabled: Fast boot enabled.
      #  - slice_hash: Slice and hash mode.
      #  - on_fly: On the fly hash.
      # Possible options: 
      fast_boot: enabled
      # --------------------------------------===== Fuse version [Optional] =====---------------------------------------
      # Description: The value must be equal or greater than the version stored in fuses to allow loading this
      # container.
      fuse_version: 0
      # ------------------------------------===== Software version [Optional] =====-------------------------------------
      # Description: Number used by Privileged Host Boot Companion (PHBC) to select between multiple images with same
      # Fuse version field.
      sw_version: 0
      # -------------------------------===== AHAB container signing key [Optional] =====--------------------------------
      # Description: Private key used for sign the container header. Header can be signed by SRK. The referenced SRK
      # must not have been revoked.
      signing_key: ../_data/keys/ecc384/srk0_ecc384.pem
      # ================================================================================================================
      #                     == Configuration of AHAB Container images (array of multiple images) ==
      # ================================================================================================================
      # ---------------------------------------===== Image array [Required] =====---------------------------------------
      # Description: Array of image entries.
      images:
        - # U-Boot ATF container definition
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x000000008A200000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # meta_data_start_cpu_id:        2
          # hash_type:                     SHA384
          # -------------------------------------===== ATF binary [Required] =====--------------------------------------
          # Description: ARM Trusted Firmware binary file.
          atf: ./bl31-imx95.bin-optee Define path to the ARM Trusted Firmware

        - # U-Boot container definition
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x0000000090200000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # meta_data_start_cpu_id:        2
          # hash_type:                     SHA384
          # ------------------------------------===== U-Boot binary [Required] =====------------------------------------
          # Description: U-Boot binary file.
          # uboot: u-boot-imx95-19x19-lpddr5-evk.bin-sd
          uboot: ./u-boot.bin Define path to the U-Boot binary file

        - # A TEE (Trusted Execution Environment) is a trusted OS running in some secure environment, for example, TrustZone on ARM CPUs, or a separate secure co-processor etc. A TEE driver handles the details needed to communicate with the TEE.
          # Image array default settings. Can be override by defines that are hidden in template:
          # load_address:                  0x000000008C000000
          # image_type:                    executable
          # core_id:                       cortex-a55
          # meta_data_start_cpu_id:        2
          # hash_type:                     SHA384
          # -----------------------------------------===== TEE [Required] =====-----------------------------------------
          # Description: TEE - Trusted Execution Environment binary
          tee: ./tee.bin Define path to the TEE (Trusted Execution Environment)

      # ================================================================================================================
      #                                      == Configuration of AHAB SRK table ==                                      
      # ================================================================================================================
      # ---------------------------------===== SRK Table [Conditionally required] =====---------------------------------
      # Description: SRK (Super Root key) table definition.
      srk_table: All attributes related to the signing
        # ----------------------------------------===== CA Flag [Optional] =====----------------------------------------
        # Description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys
        flag_ca: true
        # ------------------------------===== Super Root Key (SRK) table [Required] =====-------------------------------
        # Description: Table containing the used SRK records. All SRKs must be of the same type. Supported signing
        # algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: sha256, sha384, sha512, sha3_256,
        # sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, rsa2048, rsa4096,
        # dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just in new
        # type of AHAB container
        srk_array:
          - ../_data/keys/ecc384/srk0_ecc384.pub
          - ../_data/keys/ecc384/srk1_ecc384.pub
          - ../_data/keys/ecc384/srk2_ecc384.pub
          - ../_data/keys/ecc384/srk3_ecc384.pub

      # ================================================================================================================
      #         == Optional configuration of AHAB Container Encryption blob (if not used, erase the section) ==         
      # ================================================================================================================
      # -------------------------------------===== Encryption blob [Optional] =====-------------------------------------
      # Description: Encryption blob container definition
      # blob:
      #   # ------------------------------------===== Key identifier [Required] =====-------------------------------------
      #   # Description: The key identifier that has been used to generate DEK keyblob.
      #   key_identifier: 0
      #   # -------------------------------------===== DEK key size [Required] =====--------------------------------------
      #   # Description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size)
      #   # Possible options: <128, 192, 256>
      #   dek_key_size: 128
      #   # ----------------------------------------===== DEK key [Required] =====----------------------------------------
      #   # Description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted
      #   dek_key: my_dek_key.txt
      #   # --------------------------------------===== DEK keyblob [Optional] =====--------------------------------------
      #   # Description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted.
      #   # If NOT used, the empty keyblob is inserted into container and need to be updated later.
      #   dek_keyblob: my_wrapped_key.txt

2.6 Exporting of full AHAB image (container set)

U-Boot image consist from two image container sets. The first one contains ELE firmware, DDR firmware with OEI, system manager and U-Boot SPL. This image is loaded using the SDPS protocol. Once the U-Boot SPL is loaded to OCRAM the fastboot is opened and the second container is loaded using the fastboot protocol.

If the image is intended for loading using the UUU, the memory type should be set to serial_downloader. However the type of each individual AHAB should be set to standard, because it will be stored in flash memory.

nxpimage -v bootable-image merge -c u-boot-flash_template.yaml -o flash.bin

YamlDiffWidget("inputs/mx95_signed_ahab_bimg.diffc").html

nxpimage bootable-image get-templates -f mimx9596 -o workspace --force 
Creating workspace/bootimg_mimx9596_serial_downloader.yaml template file.
Creating workspace/bootimg_mimx9596_flexspi_nor.yaml template file.
Creating workspace/bootimg_mimx9596_emmc.yaml template file.
Creating workspace/bootimg_mimx9596_sd.yaml template file.
Creating workspace/bootimg_mimx9596_recovery_spi.yaml template file.

Configuration Differences

Show Diff Download Config

# =====================  Bootable Image Configuration template for mimx9596 / Serial downloader.  ======================

# ======================================================================================================================
#                                                 == General Options ==                                                 
# ======================================================================================================================
# -------------------------------------===== The chip family name [Required] =====--------------------------------------
# Description: NXP chip family identifier.
# Possible options: 
# kw47b42zb6, kw47b42zb7, kw47z42082, kw47z42092, kw47z420b2, kw47z420b3, lpc5502, lpc5504, lpc5506, lpc5512, lpc5514,
# lpc5516, lpc5526, lpc5528, lpc5534, lpc5536, lpc55s04, lpc55s06, lpc55s14, lpc55s16, lpc55s26, lpc55s28, lpc55s36,
# lpc55s66, lpc55s69, mc56f81646, mc56f81648, mc56f81666, mc56f81668, mc56f81746, mc56f81748, mc56f81766, mc56f81768,
# mcxa132, mcxa133, mcxa142, mcxa143, mcxa144, mcxa145, mcxa146, mcxa152, mcxa153, mcxa154, mcxa155, mcxa156, mcxa165,
# mcxa166, mcxa175, mcxa176, mcxa275, mcxa276, mcxn235, mcxn236, mcxn546, mcxn547, mcxn946, mcxn947, mcxw235, mcxw236,
# mcxw716a, mcxw716c, mcxw727a, mcxw727c, mcxw727d, mimx8ulp, mimx9131, mimx9352, mimx943, mimx9596, mimxrt1010,
# mimxrt1015, mimxrt1020, mimxrt1024, mimxrt1040, mimxrt1043, mimxrt1046, mimxrt1050, mimxrt1060, mimxrt1064,
# mimxrt1165, mimxrt1166, mimxrt1171, mimxrt1172, mimxrt1173, mimxrt1175, mimxrt1176, mimxrt1181, mimxrt1182,
# mimxrt1187, mimxrt1189, mimxrt533s, mimxrt555s, mimxrt595s, mimxrt685s, mimxrt735s, mimxrt758s, mimxrt798s, mwct2012,
# mwct2012a, nhs52s04, rw610, rw612>
family: mimx9596
# -----------------------------------------===== MCU revision [Optional] =====------------------------------------------
# Description: Revision of silicon. The 'latest' name, means most current revision.
# Possible options: 
revision: latest
revision: a1
# ------------------------------------------===== Memory type [Required] =====------------------------------------------
# Description: Specify type of memory used by bootable image description.
memory_type: serial_downloader
# ----------------------------------------===== Initial segment [Optional] =====----------------------------------------
# Description: The segment name or the index of initial segment in exported image
init_offset: 0
# ======================================================================================================================
#                                      == Primary Executable Segment definition ==                                      
# ======================================================================================================================
# ----------------------------------===== Primary Image Container Set [Optional] =====----------------------------------
# Description: This is primary Image Container Set that is validated by ROM and usually contains DDR initialization and
# SPL code. It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. In case that
# YAML configuration file is used, the Bootable image tool build the AHAB itself.
primary_image_container_set: primary_image_container_set.yaml path to our signed primary container set configuration/binary
primary_image_container_set: ../outputs/primary_signed_ahab.bin
# ======================================================================================================================
#                                     == Secondary Executable Segment definition ==                                     
# ======================================================================================================================
# ---------------------------------===== Secondary Image Container Set [Optional] =====---------------------------------
# Description: This is secondary AHAB image that is validated by SPL from primary image. It could be used as pre-
# prepared binary form of AHAB and also YAML configuration file for AHAB. In case that YAML configuration file is used,
# the Bootable image tool build the AHAB itself.
secondary_image_container_set: secondary_image_container_set.yaml path to our signed secondary container set configuration/binary
secondary_image_container_set: ../outputs/secondary_signed_ahab.bin

# Copyright 2024 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
# =======================  Bootable Image Configuration template for mimx9596 / serial_downloader.  ========================

# ======================================================================================================================
#                                                 == General Options ==
# ======================================================================================================================
# ------------------------------------------===== MCU family [Required] =====-------------------------------------------
# Description: MCU family name.
family: mimx9596
# -------------------------------------===== Chip silicon revision [Optional] =====-------------------------------------
# Description: If needed this could be used to specify silicon revision of device.
# Possible options: 
revision: a1
# ------------------------------------------===== Memory type [Required] =====------------------------------------------
# Description: Specify type of memory used by bootable image description.
memory_type: serial_downloader
# ======================================================================================================================
#                                      == Primary executable Segment definition ==
# ======================================================================================================================
# ------------------------------------===== Primary AHAB container [Optional] =====-------------------------------------
# Description: This is primary AHAB image that is validated by ROM and usually contains DDR initialization and SPL code.
# AHAB container image path. It could be used as pre-prepared binary form of AHAB and also YAML configuration file for
# AHAB. In case that YAML configuration file is used, the Bootable image tool build the AHAB itself.
primary_image_container_set: ../outputs/primary_signed_ahab.bin path to our signed primary container set configuration/binary
# ======================================================================================================================
#                                     == Secondary executable Segment definition ==
# ======================================================================================================================
# -----------------------------------===== Secondary AHAB container [Optional] =====------------------------------------
# Description: This is secondary AHAB image that is validated by SPL from primary image. AHAB container image path. It
# could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. In case that YAML
# configuration file is used, the Bootable image tool build the AHAB itself.
secondary_image_container_set: ../outputs/secondary_signed_ahab.bin path to our signed secondary container set configuration/binary

U_BOOT_PRIMARY = "inputs/mx95_signed_uboot_primary.yaml"
U_BOOT_SECONDARY = "inputs/mx95_signed_uboot_secondary.yaml"
U_BOOT_FLASH_BOOT_CFG = "inputs/bootimg_signed_mx95_serial_downloader.yaml"
U_BOOT_FLASH_BOOT = "outputs/flash.bin"

VERBOSITY = "-v"

# EXPORT PRIMARY AHAB IMAGE
%! nxpimage $VERBOSITY ahab export --config $U_BOOT_PRIMARY

nxpimage -v ahab export --config inputs/mx95_signed_uboot_primary.yaml 
INFO:spsdk.apps.nxpimage:Created AHAB Image:
Name:      AHAB Image
Starts:    0x0
Ends:      0xe2fff
Size:      Size: 908.0 kiB; 929,792 B
Alignment: 512 B
Execution Start Address: Not defined
Pattern:zeros
AHAB Image for mimx9596_a1

INFO:spsdk.apps.nxpimage:Created AHAB Image memory map:

+==0x0000_0000= AHAB Image ==========================+
|             Size: 908.0 kiB; 929,792 B             |
|             AHAB Image for mimx9596_a1             |
|                   Pattern: zeros                   |
|+==0x0000_0000= AHAB Containers ===================+|
||              Size: 8.0 kiB; 8,192 B              ||
||              AHAB Containers block               ||
||                  Pattern: zeros                  ||
||+==0x0000_0000= AHAB Container 0 ================+||
|||                  Size: 544 B                   |||
|||         AHAB Container for nxp_SWver:0         |||
||+==0x0000_021f===================================+||
||                    Gap: 480 B                    ||
||+==0x0000_0400= AHAB Container 1 ================+||
|||                  Size: 832 B                   |||
|||         AHAB Container for oem_SWver:0         |||
||+==0x0000_073f===================================+||
||                    Gap: 192 B                    ||
||+==0x0000_0800= AHAB Container 2 ================+||
|||             Size: 1.3 kiB; 1,344 B             |||
|||         AHAB Container for oem_SWver:0         |||
||+==0x0000_0d3f===================================+||
|+==0x0000_1fff=====================================+|
|+==0x0000_2000= Container 0 AHAB Data Image 0 =====+|
||            Size: 104.6 kiB; 107,072 B            ||
||  AHAB encrypted data block for ele core and ele  ||
||                   Image Type.                    ||
|+==0x0001_c23f=====================================+|
|                   Gap: 15.4 kiB                    |
|+==0x0002_0000= Container 1 AHAB Data Image 0 =====+|
||             Size: 56.0 kiB; 57,344 B             ||
||  AHAB data block for v2x-1 core and v2x_primary  ||
||                   Image Type.                    ||
|+==0x0002_dfff=====================================+|
|+==0x0002_e000= Container 1 AHAB Data Image 1 =====+|
||             Size: 28.0 kiB; 28,672 B             ||
|| AHAB data block for v2x-2 core and v2x_secondary ||
||                   Image Type.                    ||
|+==0x0003_4fff=====================================+|
|+==0x0003_5000= OEI DDR ===========================+|
||            Size: 315.0 kiB; 322,560 B            ||
||AHAB data block for cortex-m33 core and oei Image ||
||                      Type.                       ||
|+==0x0008_3bff=====================================+|
|                   Gap: 64.0 kiB                    |
|+==0x0009_3c00= OEI TCM ===========================+|
||              Size: 5.0 kiB; 5,120 B              ||
||AHAB data block for cortex-m33 core and oei Image ||
||                      Type.                       ||
|+==0x0009_4fff=====================================+|
|+==0x0009_5000= System manager ====================+|
||            Size: 151.0 kiB; 154,624 B            ||
||AHAB data block for cortex-m33 core and executable||
||                   Image Type.                    ||
|+==0x000b_abff=====================================+|
|+==0x000b_ac00= Additional Cortex M7 application ==+|
||             Size: 15.0 kiB; 15,360 B             ||
||     AHAB data block for cortex-m7-1 core and     ||
||              executable Image Type.              ||
|+==0x000b_e7ff=====================================+|
|+==0x000b_e800= U-Boot SPL ========================+|
||            Size: 146.0 kiB; 149,504 B            ||
||AHAB data block for cortex-a55 core and executable||
||                   Image Type.                    ||
|+==0x000e_2fff=====================================+|
|+==0x000e_3000= V2X core Dummy record =============+|
||                    Size: 0 B                     ||
||AHAB data block for cortex-m33 core and v2x_dummy ||
||                   Image Type.                    ||
|+==0x000e_2fff=====================================+|
+==0x000e_2fff=======================================+

Success. (AHAB: outputs/primary_signed_ahab.bin created.)
Generated file containing SRK hash: outputs/primary_signed_ahab_oem2_srk0_hash.txt
INFO:spsdk.image.ahab.utils:
Fuses info:

 --== Grouped register name: SRKH ==-- 
OTP ID: 128, Value: 0xc0b2eb69
OTP ID: 129, Value: 0xb1801c9f
OTP ID: 130, Value: 0x97c6d49f
OTP ID: 131, Value: 0xb2580b27
OTP ID: 132, Value: 0x8703c1a4
OTP ID: 133, Value: 0xdf20e0ea
OTP ID: 134, Value: 0xdc7f62d9
OTP ID: 135, Value: 0xea117f8e

Generated script for writing fuses for container 2: outputs/primary_signed_ahab_oem2_srk0_hash_nxpele.bcf

# EXPORT SECONDARY AHAB IMAGE
%! nxpimage $VERBOSITY ahab export --config $U_BOOT_SECONDARY

nxpimage -v ahab export --config inputs/mx95_signed_uboot_secondary.yaml 
INFO:spsdk.apps.nxpimage:Created AHAB Image:
Name:      AHAB Image
Starts:    0x0
Ends:      0x196fff
Size:      Size: 1.6 MiB; 1,667,072 B
Alignment: 512 B
Execution Start Address: Not defined
Pattern:zeros
AHAB Image for mimx9596_a1

INFO:spsdk.apps.nxpimage:Created AHAB Image memory map:

+==0x0000_0000= AHAB Image ====================================+
|                  Size: 1.6 MiB; 1,667,072 B                  |
|                  AHAB Image for mimx9596_a1                  |
|                        Pattern: zeros                        |
|+==0x0000_0000= AHAB Containers =============================+|
||                   Size: 8.0 kiB; 8,192 B                   ||
||                   AHAB Containers block                    ||
||                       Pattern: zeros                       ||
||+==0x0000_0000= AHAB Container 0 ==========================+||
|||                       Size: 960 B                        |||
|||              AHAB Container for oem_SWver:0              |||
||+==0x0000_03bf=============================================+||
|+==0x0000_1fff===============================================+|
|+==0x0000_2000= ATF - ARM Trusted Firmware ==================+|
||                  Size: 38.0 kiB; 38,912 B                  ||
||  AHAB data block for cortex-a55 core and executable Image  ||
||                           Type.                            ||
|+==0x0000_b7ff===============================================+|
|+==0x0000_b800= U-Boot Firmware =============================+|
||                 Size: 1.0 MiB; 1,091,584 B                 ||
||  AHAB data block for cortex-a55 core and executable Image  ||
||                           Type.                            ||
|+==0x0011_5fff===============================================+|
|+==0x0011_6000= U-Boot TEE - Trusted Execution Environment ==+|
||                 Size: 516.0 kiB; 528,384 B                 ||
||  AHAB data block for cortex-a55 core and executable Image  ||
||                           Type.                            ||
|+==0x0019_6fff===============================================+|
+==0x0019_6fff=================================================+

Success. (AHAB: outputs/secondary_signed_ahab.bin created.)
Generated file containing SRK hash: outputs/secondary_signed_ahab_oem0_srk0_hash.txt
INFO:spsdk.image.ahab.utils:
Fuses info:

 --== Grouped register name: SRKH ==-- 
OTP ID: 128, Value: 0xc0b2eb69
OTP ID: 129, Value: 0xb1801c9f
OTP ID: 130, Value: 0x97c6d49f
OTP ID: 131, Value: 0xb2580b27
OTP ID: 132, Value: 0x8703c1a4
OTP ID: 133, Value: 0xdf20e0ea
OTP ID: 134, Value: 0xdc7f62d9
OTP ID: 135, Value: 0xea117f8e

Generated script for writing fuses for container 0: outputs/secondary_signed_ahab_oem0_srk0_hash_nxpele.bcf

# EXPORT U-BOOT IMAGE
%! nxpimage $VERBOSITY bootable-image merge --config $U_BOOT_FLASH_BOOT_CFG --output $U_BOOT_FLASH_BOOT

nxpimage -v bootable-image merge --config inputs/bootimg_signed_mx95_serial_downloader.yaml --output outputs/flash.bin 
INFO:spsdk.apps.nxpimage:Created Bootable Image:
Name:      Bootable Image for mimx9596
Starts:    0x0
Ends:      0x279fff
Size:      Size: 2.5 MiB; 2,596,864 B
Alignment: 1 B
Execution Start Address: Not defined
Pattern:zeros
Memory type: MemoryType.SERIAL_DOWNLOADER
Revision: a1

INFO:spsdk.apps.nxpimage:Created Bootable Image memory map:

+==0x0000_0000= Bootable Image for mimx9596 ======+
|           Size: 2.5 MiB; 2,596,864 B            |
|    Memory type: MemoryType.SERIAL_DOWNLOADER    |
|                  Revision: a1                   |
|                 Pattern: zeros                  |
|+==0x0000_0000= primary_image_container_set ====+|
||          Size: 908.0 kiB; 929,792 B           ||
|+==0x000e_2fff==================================+|
|+==0x000e_3000= secondary_image_container_set ==+|
||          Size: 1.6 MiB; 1,667,072 B           ||
|+==0x0027_9fff==================================+|
+==0x0027_9fff====================================+

Success. (Bootable Image: outputs/flash.bin created) 

3 Download image

3.1 Download AHAB image

Set the boot mode to Cortex-M Serial Downloader (1001 on EVK boot switch) and download the files using the UUU tool

%! nxpuuu $VERBOSITY write -f mimx9596 -b emmc $U_BOOT_FLASH_BOOT

nxpuuu -v write -f mimx9596 -b emmc outputs/flash.bin 
SDPS: boot -f outputs/flash.bin


SDPV: write -f outputs/flash.bin -skipspl


SDPV: jump


Done

4. Write fuses

We need to write SRKH (Super root key hash) to fuses. This might be done using the nxpele tool. When the signed AHAB Image is exported, the “.bcf” script is generated.

The script might look like this:

# nxpele AHAB SRK fuses programming script
# Generated by SPSDK 2.6.0.dev45+gbb9e767b
# Family: mimx9596 Revision: a1

# Value: 0x69ebb2c09f1c80b19fd4c697270b58b2a4c10387eae020dfd9627fdc8e7f11ea
# Description: SHA256 hash digest of hash of four SRK keys
# Grouped register name: SRKH

# OTP ID: 128, Value: 0xc0b2eb69
write-fuse --index 128 --data 0xC0B2EB69
# OTP ID: 129, Value: 0xb1801c9f
write-fuse --index 129 --data 0xB1801C9F
# OTP ID: 130, Value: 0x97c6d49f
write-fuse --index 130 --data 0x97C6D49F
# OTP ID: 131, Value: 0xb2580b27
write-fuse --index 131 --data 0xB2580B27
# OTP ID: 132, Value: 0x8703c1a4
write-fuse --index 132 --data 0x8703C1A4
# OTP ID: 133, Value: 0xdf20e0ea
write-fuse --index 133 --data 0xDF20E0EA
# OTP ID: 134, Value: 0xdc7f62d9
write-fuse --index 134 --data 0xDC7F62D9
# OTP ID: 135, Value: 0xea117f8e
write-fuse --index 135 --data 0xEA117F8E

The script might be executed using nxpele batch command:

nxpele -f mimx9596 batch ./outputs/primary_signed_ahab_oem2_srk0_hash_nxpele.bcf

5. Boot and test

Now change the boot mode to Cortex-M eMMC (1010 on EVK boot switch) and reset the board. Find the serial port that belongs to U-Boot console and interrupt the boot. When the console is switched to U-Boot menu, we can use the nxpele tool to communicate with the ELE.

%! nxpele -f mimx9596 -p COM138 -d uboot_serial get-info

nxpele -f mimx9596 -p COM138 -d uboot_serial get-info 
ELE get info ends successfully:
Command:          0xda
Version:          2
Length:           160
SoC ID:           MX95 - 0x9500
SoC version:      A100
Life Cycle:       OEM_CLSD - 0x0040
SSSM state:       4
UUID:             8225b4b22ee24782b66bce6f05c08d1f
SHA256 ROM PATCH: 2063bc6261856eb33e2962120641cd099a83c80393fa6a31d66b36960dcaf727
SHA256 FW:        36d658981d5cb8ec5bea4bd57b5a4231ccf8b95489efc965d383b1ca844e6135
Advanced information:
  OEM SRKH:       69ebb2c09f1c80b19fd4c697270b58b2a4c10387eae020dfd9627fdc8e7f11ea
  IMEM state:     This is non-existing tag(0x0) from enum: EleImemState - 0x00
  CSAL state:     EdgeLock secure enclave random context initialization succeed - 0x02
  TRNG state:     TRNG entropy is valid and ready to be read - 0x03
  OEM PQC SRKH:  00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000